Mechanisms for performing sequential equivalence checking for asynchronous verification
are provided. A first model of the integrated circuit design is provided that has additional …

An apparatus includes a processor to: receive a request to perform a job flow defined in a
job flow definition; retrieve the most recent versions of a set of task routines to perform a set …

Techniques for performing static and dynamic race logic analysis on an integrated circuit
(IC) are described herein. According to one aspect of the invention, HDL (hardware …

The automatic verification of designs of digital circuits for their equivalence, wherein logic
designs implemented in dif ferent hardware description languages (HDLs) and different …

The present disclosure provides a method, apparatus and configurationarrangement for
configuring an intelligent elec tronic device, in which a group of function blocks defining at …

An apparatus includes a processor to: receive a request to generate a superset job flow
replacing multiple job flows including an output job flow and preceding job flows previously …

The command and control module controls the overall rout ing process of the nets in a circuit
and includes at least one director to invoke at least one routing engine to achieve com …

In various implementations of the invention, methods and apparatuses are provided that
enable timing accurate, bit level hardware models for simulation at a rapid rate. With various …

An apparatus includes a processor to: receive a job flow definition; retrieve the most recent
versions of a set of task routines for the defined job flow; translate, into an intermediate …

Pat. No. 10,002,029, which is continuation-in-part of application No. 15/851,869, filed on
Dec. 22, 2017, now Pat. No. 10,078,710, which is continuation of application No …