Drain current model for double gate tunnel-FETs with InAs/Si heterojunction and source-pocket architecture
H Lu, B Lu, Y Zhang, Y Zhang, Z Lv - nanomaterials, 2019 - mdpi.com
The practical use of tunnel field-effect transistors is retarded by the low on-state current. In
this paper, the energy-band engineering of InAs/Si heterojunction and novel device structure …
this paper, the energy-band engineering of InAs/Si heterojunction and novel device structure …
Structural Process Variation on Silicon Nanotube Tunnel Field-Effect Transistor
P Rajendiran, A Nisha Justeena - Silicon, 2023 - Springer
In this manuscript, we have investigated the geometrical process variation of a 3-dimensinal
silicon nanotube tunnel field effect transistor (Silicon NT-TFET) using TCAD numerical …
silicon nanotube tunnel field effect transistor (Silicon NT-TFET) using TCAD numerical …
Soft error analysis on junctionless ringFET structures and junctionless ringFET-based inverter circuits using numerical device modeling
M Ramya, KK Nagarajan - Microelectronics Reliability, 2024 - Elsevier
The performance of junctionless ringFETs under heavy ion irradiation is investigated
utilizing 3D TCAD simulations. The vulnerable location of the ringFET device is identified by …
utilizing 3D TCAD simulations. The vulnerable location of the ringFET device is identified by …
Sensitivity analysis of junctionless silicon NT-TFET and performance metrics comparison with the silicon NT-TFET
P Rajendiran, AN Justeena, J Mrabet… - Journal of Nanoparticle …, 2024 - Springer
In this article, we investigated the sensitivity of the junctionless silicon nanotube tunnel field-
effect transistor (JLSiNT-TFET). To accomplish this, we utilized the Sentaurus TCAD …
effect transistor (JLSiNT-TFET). To accomplish this, we utilized the Sentaurus TCAD …
Design and Compressive Analysis of Junctionless Multigate FinFET Towards Low Power and High Frequency Applications
ES Kumar, PS Kumar - Silicon, 2022 - Springer
Advances in microelectronics have enabled smaller technical nodes, lower threshold
voltages, and greater working frequencies. Even though VLSI circuit performance and power …
voltages, and greater working frequencies. Even though VLSI circuit performance and power …
Silicon nanotube SRAM and its SEU reliability
GD Jayakumar, R Srinivasan - Superlattices and Microstructures, 2017 - Elsevier
In this work, silicon nanotube FET (SiNT FET) based 6T SRAM cell operation is
demonstrated and its Read, Write and Hold SNMs (static noise margin) are analyzed. The …
demonstrated and its Read, Write and Hold SNMs (static noise margin) are analyzed. The …
Reconfigurable silicon nanotube using numerical simulations
AN Justeena, R Ambika, P Sadagopan… - Journal of …, 2020 - Springer
Device reconfigurability refers to the ability to choose N or P type for the same structure.
Such reconfigurable operation is demonstrated herein for a silicon nanotube (SiNT) …
Such reconfigurable operation is demonstrated herein for a silicon nanotube (SiNT) …
[PDF][PDF] An innovative method for estimating optimal Gate work function and dielectric constant of a nanoscale DG-TFET based on analytical modeling of tunneling …
F Khorramrouz, SAS Ziabari, A Heydari - Journal of Nanoanalysis, 2021 - journals.iau.ir
Scaling of conventional CMOS transistors according to Moore's law is facing several
challenges, such as high OFF-state current, high sub-threshold slope (SS) and other short …
challenges, such as high OFF-state current, high sub-threshold slope (SS) and other short …