Offset-canceling current-sampling sense amplifier for resistive nonvolatile memory in 65 nm CMOS

T Na, B Song, JP Kim, SH Kang… - IEEE Journal of Solid …, 2016 - ieeexplore.ieee.org
Resistive nonvolatile memory (NVM) is considered to be a leading candidate for next-
generation memory. However, maintaining a target sensing margin is a challenge with …

Body biased sense amplifier with auto-offset mitigation for low-voltage SRAMs

D Patel, A Neale, D Wright… - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
This paper proposes a Differential-Input Body Bias Sense Amplifier (DIBBSA) with an auto-
offset mitigation feature suitable for low-voltage SRAMs where the differential bitline signals …

A low-voltage SRAM sense amplifier with offset cancelling using digitized multiple body biasing

B Liu, J Cai, J Yuan, Y Hei - … on Circuits and Systems II: Express …, 2016 - ieeexplore.ieee.org
With continued CMOS technology scaling down, transistors exhibit higher degrees of
variation and mismatch, resulting in a larger offset voltage. A large offset voltage will enlarge …

0.23-V sample-boost-latch-based offset tolerant sense amplifier

D Patel, M Sachdev - IEEE Solid-State Circuits Letters, 2018 - ieeexplore.ieee.org
An offset tolerant SRAM sense amplifier (SA) deployed with sample-boost-latch technique to
facilitate both common mode and differential mode boosting is proposed. The common …

A double-tail sense amplifier for low-voltage SRAM in 28nm technology

PF Chiu, B Zimmer, B Nikolić - 2016 IEEE Asian Solid-State …, 2016 - ieeexplore.ieee.org
A double-tail sense amplifier (DTSA) is designed as a drop-in replacement for a
conventional SRAM sense amplifier (SA), to enable a robust read operation at low voltages …

A 0.4 µA Offset, 6ns Sensing-time Multi-level Sense Amplifier for Resistive Non-Volatile Memories in 65nm LSTP Technology

F Husain, B Iqbal, A Grover - … on VLSI Design and 2021 20th …, 2021 - ieeexplore.ieee.org
Physical limitations in scaling of Non-Volatile Memories (NVMs) necessitates alternative
ways to increase on-chip storage density and reduce cost. New technologies like MRAMs …

A dual-data line read scheme for high-speed low-energy resistive nonvolatile memories

A Lee, H Lee, F Ebrahimi, B Lam… - … Transactions on Very …, 2017 - ieeexplore.ieee.org
Resistance-based memory devices are considered as a strong candidate for next-
generation nonvolatile memories as well as potential application in high density embedded …

A capacitor-coupled stacked-based sense amplifier with enhanced offset tolerance for low power SRAM

P Zhao, H Zhao, J Yin, Z Li, S Qiao - IEICE Electronics Express, 2023 - jstage.jst.go.jp
A capacitor-coupled stacked-based sense amplifier (CC-STSA) is proposed to compensate
the input-referred offset voltage (VOS), which dictates the minimum required bitline swing for …

Evaluating Sense Amplifier Performance in SRAM Circuits

M Gupta, R Jha, R Kumari… - 2023 3rd International …, 2023 - ieeexplore.ieee.org
Examining sense amplifiers is vital to enhance circuit efficiency, optimize reads, minimize
power usage, and elevate system functionality through precise signal detection and faster …

Comparative Study of Single, Regular and Flip Well Subthreshold SRAMs in 22 nm FDSOI Technology

SH Zadeh, T Ytterdal, S Aunet - 2020 IEEE Nordic Circuits and …, 2020 - ieeexplore.ieee.org
This study presents a comparative study of single, regular and flip well subthreshold SRAMs
in 22 nm FDSOI technology. A 7T loadless SRAM cell with a decoupled read and write port …