An asynchronous 6 bit 1 GS/s ADC is achieved by time interleaving two ADCs based on the
binary successive approximation (SA) algorithm using a series capacitive ladder. The semi …

There is a growing need to understand and combat potential radiation damage problems in
semiconductor devices and circuits. Assessing the billion-dollar market for detection …

Time-interleaved (TI) analog-to-digital converters (ADCs) are frequently advocated as a
power-efficient solution to realize the high sampling rates required in single-chip …

The Emerging biomedical applications such as electrocardiography, electroencephalogram,
wireless implantable devices have required optimized power-based SAR ADC in them to …

In this paper we present a novel successive approximation register (SAR) analog-to-digital
converter (ADC) designed for the applications that demand many such converters working in …

This paper describes a 10-bit 2.5 Msample/s successive approximation analog-to-digital
converter (ADC) for SoC system. Based on conventional successive approximation ADC …

With reference to an architecture for the full integration of a 60 GHz receiver in embedded
systems with wireless gigabit connectivity, the paper presents the design of key building …

Analog-to-Digital Converter (ADC) technology has been advancing to achieve a balance
between speeds, size and cost. Successive approximation register (SAR) ADC is very …

SAR ADC 适合工作在中级转换速度(MSPS, GSPS), 是低功耗和高精度的信号处理应用的最佳
选择. 为了更好地指导折中设计, 基于梳理传统SAR ADC 的FoM (figure of merits) …

BACKGROUND There is unrelenting market demand for circuits that are Smaller Ze, use
less power, are faster, and are easily Scalable when compared to conventional devices …