A summary-attainment-surface plotting method for visualizing the performance of stochastic multiobjective optimizers
J Knowles - 5th International Conference on Intelligent Systems …, 2005 - ieeexplore.ieee.org
When evaluating the performance of a stochastic optimizer it is sometimes desirable to
express performance in terms of the quality attained in a certain fraction of sample runs. For …
express performance in terms of the quality attained in a certain fraction of sample runs. For …
Variable input delay cmos logic for low power design
T Raja, VD Agrawal, ML Bushnell - IEEE transactions on very …, 2009 - ieeexplore.ieee.org
We propose a new complementary metal-oxide semiconductor (CMOS) gate design that has
different delays along various input to output paths within the gate. The delays are …
different delays along various input to output paths within the gate. The delays are …
A system-level methodology for fast multi-objective design space exploration
In this paper, we address the problem of the efficient exploration of the architectural design
space for parameterized systems. Since the design space is multi-objective, our aim is to …
space for parameterized systems. Since the design space is multi-objective, our aim is to …
Dual-threshold voltage design of sub-threshold circuits
J Yao - 2014 - search.proquest.com
Threshold voltage of MOSFET technology represents the value of the gate-source voltage
when the current in a MOS transistor starts to increase significantly since the conduction …
when the current in a MOS transistor starts to increase significantly since the conduction …
Minimum dynamic power CMOS circuit design by a reduced constraint set linear program
T Raja, VD Agrawal, ML Bushnell - … International Conference on …, 2003 - ieeexplore.ieee.org
In the previous work, the problem of finding gate delays to eliminate glitches has been
solved by linear programs (LP) requiring an exponentially large number of constraints. By …
solved by linear programs (LP) requiring an exponentially large number of constraints. By …
CMOS leakage and glitch minimization for power-performance tradeoff
Y Lu, VD Agrawal - Journal of Low Power Electronics, 2006 - ingentaconnect.com
A mixed integer linear programming (MILP) technique simultaneously minimizes the
leakage and glitch power consumption of a static CMOS circuit for any specified input to …
leakage and glitch power consumption of a static CMOS circuit for any specified input to …
Variable input delay CMOS logic for low power design
T Raja, VD Agrawal, ML Bushnell - … International Conference on …, 2005 - ieeexplore.ieee.org
Modern digital circuits consist of logic gates implemented in the complementary metal oxide
semiconductor (CMOS) technology. The time taken for a logic gate output to change after …
semiconductor (CMOS) technology. The time taken for a logic gate output to change after …
Glitch power reduction via clock skew scheduling
A Vijayakumar, S Kundu - 2014 IEEE Computer Society Annual …, 2014 - ieeexplore.ieee.org
Dynamic power consumption is directly related tothe number of the signal transitions in a
circuit. Glitches are undesired spurious transitions caused by inputs of a gate arriving at …
circuit. Glitches are undesired spurious transitions caused by inputs of a gate arriving at …
Glitch elimination by gate freezing, gate sizing and buffer insertion for low power optimization circuit
H Lee, H Shin, J Kim - 30th Annual Conference of IEEE …, 2004 - ieeexplore.ieee.org
One of the major factors contributing to the power dissipation in CMOS digital circuits is the
switching activity. Many of such switching activities include spurious pulses, called glitches …
switching activity. Many of such switching activities include spurious pulses, called glitches …
[PDF][PDF] CMOS Circuit Design for Minimum Dynamic Power and Highest Speed.
T Raja, VD Agrawal, ML Bushnell - VLSI Design, 2004 - Citeseer
Abstract {A new low-power design method produces CMOS circuits that consume the least
dynamic power at the highest speed permitted under the technology constraint. A gate is …
dynamic power at the highest speed permitted under the technology constraint. A gate is …