A review of system-in-package technologies: application and reliability of advanced packaging

H Wang, J Ma, Y Yang, M Gong, Q Wang - Micromachines, 2023 - mdpi.com
The system-in-package (SiP) has gained much interest in the current rapid development of
integrated circuits (ICs) due to its advantages of integration, shrinking, and high density. This …

Recent advances and trends in multiple system and heterogeneous integration with TSV-less interposers

JH Lau - IEEE Transactions on Components, Packaging and …, 2022 - ieeexplore.ieee.org
In this study, the recent advances and trends in multiple system and heterogeneous
integration with through-silicon via (TSV)-less interposer (organic interposer or 2.3-D IC …

[图书][B] Chiplet design and heterogeneous integration packaging

JH Lau - 2023 - Springer
There are at least five different chiplet design and heterogeneous integration packaging,
namely (1) chip partition and heterogeneous integration (driven by cost and technology …

Thermal modeling of a chiplet-based packaging with a 2.5-D through-silicon via interposer

M Zhou, L Li, F Hou, G He, J Fan - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
Chiplet-based packaging technology integrates multiple heterogeneous dies with different
functions and materials into a single system as a LEGO-based approach using advanced …

Fundamental Insights into Copper-Epoxy Interfaces for High-Frequency Chip-to-Chip Interconnects

J Park, M Dauda, M Bello, I Agbadan… - … Applied Materials & …, 2024 - ACS Publications
Future processes and materials are needed to enable multichip packages with chip-to-chip
(C2C) data rates of 50 GB/s or higher. This presents a fundamental challenge because of …

System technology co-optimization for advanced integration

S Pal, A Mallik, P Gupta - Nature Reviews Electrical Engineering, 2024 - nature.com
Advanced integration and packaging will drive the scaling of computing systems in the next
decade. Diversity in performance, cost and scale of the emerging systems implies that …

Silicon wafer CMP slurry using a hydrolysis reaction accelerator with an amine functional group remarkably enhances polishing rate

JY Bae, MH Han, SJ Lee, ES Kim, K Lee, G Lee… - Nanomaterials, 2022 - mdpi.com
Recently, as an alternative solution for overcoming the scaling-down limitations of logic
devices with design length of less than 3 nm and enhancing DRAM operation performance …

[图书][B] Flip Chip, Hybrid Bonding, Fan-in, and Fan-out Technology

JH Lau - 2024 - Springer
Flip chip is one of the chip-level interconnects and has been used for highperformance and
high-density applications such as central processing unit, graphic processing unit, and …

Overlay challenges in 3D heterogeneous integration

Y Grauer, A Miller, DC La Tulipe… - Metrology …, 2022 - spiedigitallibrary.org
3D heterogeneous integration is an evolving segment of the world semiconductor industry
roadmap to enable improvements in device performance beyond Moore's law expectations …

Study of Fabrication and Reliability for the extremely large 2.5 D advanced Package

K Murai, H Onozeki, D Kang, K Hirano… - 2023 IEEE 73rd …, 2023 - ieeexplore.ieee.org
Today, various heterogeneously integrated package structures have been studying, for
example, 2.1 D, 2.3 D, and 2.5 D advanced package. Especially, the 2.5 D package using …