Machine learning for agile fpga design
Field-programmable gate arrays (FPGAs) have become popular means of hardware
acceleration since they offer massive parallelism, flexible configurability, and potentially …
acceleration since they offer massive parallelism, flexible configurability, and potentially …
Machine learning for FPGA electronic design automation
A Biscontini, E Popovici, A Temko - IEEE Access, 2024 - ieeexplore.ieee.org
In the last decades, field-programmable gate arrays (FPGAs) have become increasingly
important to the electronics industry, offering higher performance and lower power …
important to the electronics industry, offering higher performance and lower power …
Lay-Net: Grafting Netlist Knowledge on Layout-Based Congestion Prediction
Congestion modeling is a key point for improving the routability of VLSI placement solutions.
The underuti-lization of netlist information limits the performance of ex-isting layout-based …
The underuti-lization of netlist information limits the performance of ex-isting layout-based …
Efficient Detailed Routing for FPGA Back-End Flow Using Reinforcement Learning
Over the past few years, the computation capability of field-programmable gate arrays
(FPGAs) has increased tremendously. This has led to the increase in the complexity of the …
(FPGAs) has increased tremendously. This has led to the increase in the complexity of the …
A deep-learning framework for predicting congestion during FPGA placement
D Maarouff, A Shamli, T Martin… - … Conference on Field …, 2020 - ieeexplore.ieee.org
The ability to quickly and accurately predict congestion has emerged as one of the most
critical problems during placement. In this paper, we present DLCong, a deep learning …
critical problems during placement. In this paper, we present DLCong, a deep learning …
Mitigating distribution shift for congestion optimization in global placement
The placement and routing (PnR) flow plays a critical role in physical design. Poor routing
congestion is a possible problem causing severe routing detours, which can lead to …
congestion is a possible problem causing severe routing detours, which can lead to …
Predicting routability of FPGA design by learning complex network images
T Nie, Y Wang, P Liu, K Zhao, Z Wang - Expert Systems with Applications, 2025 - Elsevier
Accurately and efficiently predicting the routability of modern FPGAs in the early stages is
significant for achieving ultimate optimization. We propose a novel approach for FPGA …
significant for achieving ultimate optimization. We propose a novel approach for FPGA …
[HTML][HTML] A Reinforcement Learning Based Approach for Efficient Routing in Multi-FPGA Platforms
Prototyping using multi-FPGA platforms is unique because of its use in real-world testing
and cycle-accurate information on the design. However, this is a complex and time …
and cycle-accurate information on the design. However, this is a complex and time …
Lay-Net: Grafting Netlist Knowledge on Layout-Based Congestion Prediction
Congestion modeling is crucial for enhancing the routability of VLSI placement solutions.
The underutilization of netlist information constrains the efficacy of existing layout-based …
The underutilization of netlist information constrains the efficacy of existing layout-based …
Dual Multimodal Fusions With Convolution and Transformer Layers for VLSI Congestion Prediction
H Gu, Y Wang, X Zheng, K Peng, Z Zhu… - … on Computer-Aided …, 2024 - ieeexplore.ieee.org
In very large scale integration (VLSI) circuit physical design, precise congestion prediction
during placement is crucial for enhancing routability and accelerating design processes …
during placement is crucial for enhancing routability and accelerating design processes …