Mapper tree with super leaf nodes

U Shabi, D Zalstein, R Gazit, V Shveidel - US Patent 11,068,455, 2021 - Google Patents
A mapper tree for a logical volume is provided by storing, in each leaf node of the mapper
tree, pointers to pages of non-volatile storage that store host data written to corresponding …

Graphics processor operation scheduling for deterministic latency

J Ray, S Panneer, S Tangri, B Ashbaugh… - US Patent …, 2024 - Google Patents
Embodiments described herein include software, firmware, and hardware that provides
techniques to enable deterministic scheduling across multiple general-purpose graphics …

Multi-tile architecture for graphics operations

A Koker, B Ashbaugh, S Janus… - US Patent …, 2024 - Google Patents
Embodiments are generally directed to a multi-tile architecture for graphics operations. An
embodiment of an apparatus includes a multi-tile architecture for graphics operations …

Multi-tile memory management

AR Appu, A Koker, A Anantaraman… - US Patent App. 17 …, 2022 - Google Patents
2021-08-13 Assigned to INTEL CORPORATION reassignment INTEL CORPORATION
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors …

Instructions and logic to perform floating point and integer operations for machine learning

H Kaul, MA Anders, SK Mathew, A Yao, J Ray… - US Patent …, 2024 - Google Patents
One embodiment provides for a graphics processing unit to accelerate machine-learning
operations, the graphics processing unit comprising a multiprocessor having a single …

Systems and methods for cache optimization

A Koker, J Ray, E Ould-Ahmed-Vall, A Appu… - US Patent …, 2024 - Google Patents
Abstract Systems and methods for cache utilization are disclosed. In one embodiment, a
graphics processor includes processing resources to perform graphics operations and a …

Cache structure and utilization

A Koker, L Striramassarma, A Anantaraman… - US Patent …, 2024 - Google Patents
Embodiments are generally directed to cache structure and utilization. An embodiment of an
apparatus includes one or more processors including a graphics processor; a memory for …

Multi-tile memory management for detecting cross tile access providing multi-tile inference scaling and providing page migration

L Striramassarma, P Surti, V George… - US Patent …, 2024 - Google Patents
Abstract Multi-tile Memory Management for Detecting Cross Tile Access, Providing Multi-Tile
Inference Scaling with multicasting of data via copy operation, and Providing Page Migration …

Assistance for hardware prefetch in cache access

A Koker, V George, A Anantaraman, V Andrei… - US Patent …, 2024 - Google Patents
Embodiments are generally directed to graphics processor data access and sharing. An
embodiment of an apparatus includes a circuit element to produce a result in processing of …

Processing data of a database system

JG Rooney, LG Erice, P Urbanetz, DN Bauer… - US Patent …, 2022 - Google Patents
The present disclosure relates to a method for processing data of a database system, the
database system being configured to connect to a centralized cache shared with other …