New substrate passivation method dedicated to HR SOI wafer fabrication with increased substrate resistivity

D Lederer, JP Raskin - IEEE Electron Device Letters, 2005 - ieeexplore.ieee.org
We propose in this letter a new passivation method to get rid of parasitic surface conduction
in oxidized high resistivity (HR) silicon and HR silicon-on-insulator (SOI) wafers. The method …

A low-voltage 35-GHz silicon photonic modulator-enabled 112-Gb/s transmission system

A Samani, M Chagnon, D Patel… - IEEE Photonics …, 2015 - ieeexplore.ieee.org
We present a silicon photonic traveling-wave Mach-Zehnder modulator operating near 1550
nm with a 3-dB bandwidth of 35 GHz. A detailed analysis of travelingwave electrode …

Encapsulated dies with enhanced thermal performance

TS Morris, D Jandzinski, S Parker, J Chadwick… - US Patent …, 2017 - Google Patents
The present disclosure relates to enhancing the thermal performance of encapsulated flip
chip dies. According to an exemplary process, a plurality of flip chip dies are attached on a …

RF harmonic distortion of CPW lines on HR-Si and trap-rich HR-Si substrates

CR Neve, JP Raskin - IEEE Transactions on Electron Devices, 2012 - ieeexplore.ieee.org
In this paper, the nonlinear behavior of coplanar waveguide (CPW) transmission lines
fabricated on Si and high-resistivity (HR) Si substrates is thoroughly investigated …

Effective resistivity of fully-processed SOI substrates

D Lederer, JP Raskin - Solid-State Electronics, 2005 - Elsevier
We introduce in this work a new quality factor called effective resistivity (ρeff), which is used
to characterize and fairly compare the substrate resistivity of fully processed SOI wafers. The …

Method of manufacture for a silicon-on-plastic semiconductor device with interfacial adhesion layer

JC Costa - US Patent 9,812,350, 2017 - Google Patents
(57) ABSTRACT A semiconductor device and methods for manufacturing the same are
disclosed. The semiconductor device includes a polymer substrate and an interfacial layer …

A novel metamaterial-based antenna for on-chip applications for the 72.5–81 GHz frequency range

KN Olan-Nuñez, RS Murphy-Arteaga - Scientific Reports, 2022 - nature.com
In this paper we present a novel metamaterial-based antenna simulated using HFSS. The
unit cell parameters were extracted using periodic boundary conditions and wave-port …

Monolithic integration of silicon CMOS and GaN transistors in a current mirror circuit

WE Hoke, RV Chelakara, JP Bettencourt… - Journal of Vacuum …, 2012 - pubs.aip.org
GaN high electron mobility transistors (HEMTs) were monolithically integrated with silicon
CMOS to create a functional current mirror circuit. The integrated circuit was fabricated on …

Flip chip module with enhanced properties

JC Costa, TS Morris, JH Hammond… - US Patent …, 2018 - Google Patents
A flip chip module having at least one flip chip die is disclosed. The flip chip module includes
a carrier having a top surface with a first mold compound residing on the top surface. A first …

Method for manufacturing an integrated circuit package

JC Costa, G Maxim, DRW Leipold, B Scott - US Patent 10,085,352, 2018 - Google Patents
This disclosure relates to integrated circuit (IC) packages and methods of manufacturing the
same. In one method, a printed circuit board is provided with semiconductor die. The …