Mapping techniques in multicore processors: current and future trends
Multicore systems are in demand due to their high performance thus making application
mapping an important research area in this field. Breaking an application into multiple …
mapping an important research area in this field. Breaking an application into multiple …
Heterogeneous fpga-based cost-optimal design for timing-constrained cnns
Field programmable gate array (FPGA) has been one of the most popular platforms to
implement convolutional neural networks (CNNs) due to its high performance and cost …
implement convolutional neural networks (CNNs) due to its high performance and cost …
Thermal-aware task mapping on dynamically reconfigurable network-on-chip based multiprocessor system-on-chip
Dark silicon is the phenomenon that a fraction of many-core chip has to be turned off or run
in a low-power state in order to maintain the safe chip temperature. System-level thermal …
in a low-power state in order to maintain the safe chip temperature. System-level thermal …
HRHS: A high-performance real-time hardware scheduler
D Derafshi, A Norollah, M Khosroanjam… - IEEE Transactions on …, 2019 - ieeexplore.ieee.org
This article represents an on-line time-predictable distributed hardware scheduler solution,
suitable for many-core systems. We have partitioned the Main scheduler into uniform Partial …
suitable for many-core systems. We have partitioned the Main scheduler into uniform Partial …
Noc application mapping optimization using reinforcement learning
S Jagadheesh, PV Bhanu - ACM Transactions on Design Automation of …, 2022 - dl.acm.org
Application mapping is one of the early stage design processes aimed to improve the
performance of Network-on-Chip. Mapping is an NP-hard problem. A massive amount of …
performance of Network-on-Chip. Mapping is an NP-hard problem. A massive amount of …
An IP core mapping algorithm based on neural networks
Q Chen, W Huang, Y Zhang… - IEEE Transactions on Very …, 2020 - ieeexplore.ieee.org
The IP core mapping optimization problem is an NP-hard problem in network-on-chip
design. Because of the computational complexity of an IP core mapping, the MPNN-Ptr …
design. Because of the computational complexity of an IP core mapping, the MPNN-Ptr …
SAFEPOWER project: Architecture for safe and power-efficient mixed-criticality systems
M Fakih, A Lenz, M Azkarate-Askasua, J Coronel… - Microprocessors and …, 2017 - Elsevier
With the ever increasing industrial demand for bigger, faster and more efficient systems, a
growing number of cores is integrated on a single chip. Additionally, their performance is …
growing number of cores is integrated on a single chip. Additionally, their performance is …
Co-exploration of graph neural network and network-on-chip design using automl
Recently, Graph Neural Networks (GNNs) have exhibited high efficiency in several graph-
based machine learning tasks. Compared with the neural networks for computer vision or …
based machine learning tasks. Compared with the neural networks for computer vision or …
Low-complex resource mapping heuristics for mobile and iot workloads on NoC-HMPSoC architecture
Network-on-chip-based heterogeneous multiprocessor system-on-a chip (NoC-HMPSoC) a
single board computer is extensively utilized in many real-time applications such as mobile …
single board computer is extensively utilized in many real-time applications such as mobile …
Optimal application mapping and scheduling for network-on-chips with computation in STT-RAM based router
Spin-Torque Transfer Magnetic RAM (STT-RAM), one of the emerging nonvolatile memory
(NVM) technologies explored as the replacement for SRAM memory architectures, is …
(NVM) technologies explored as the replacement for SRAM memory architectures, is …