Past research has proposed numerous hardware prefetching techniques, most of which rely
on exploiting one specific type of program context information (eg, program counter …

Machine learning algorithms have shown potential to improve prefetching performance by
accurately predicting future memory accesses. Existing approaches are based on the …

With the advent of fast processors, TPUs, accelerators, and heterogeneous architectures,
computation is no longer the only bottleneck. In fact for many applications, speed of …

The rapid development of Big Data coupled with slowing down of Moore's law has made the
memory performance a bottleneck in the von Neumann architecture. Machine learning has …

Memory system performance is a major bottleneck in large-scale graph analytics. Data
prefetching can hide memory latency; this relies on accurate prediction of memory accesses …

Memory performance is a key bottleneck in accelerating graph analytics. Existing Machine
Learning (ML) prefetchers encounter challenges with phase transitions and irregular …

With the rise of Big Data, there has been a significant effort in increasing compute power
through GPUs, TPUs, and heterogeneous architectures. As a result, many applications are …

Data Prefetching is a technique that can hide memory latency by fetching data before it is
needed by a program. Prefetching relies on accurate memory access prediction, to which …

This article introduces the first open-source FPGA-based infrastructure, MetaSys, with a
prototype in a RISC-V system, to enable the rapid implementation and evaluation of a wide …

A computing system having at least one bus, a plurality of different memory components,
and a processing device operatively coupled with the plurality of memory components …