We present AVR, a push-button model checker for verifying state transition systems directly
at the source-code level. AVR uses information embedded in the word-level syntax of the …

Modern static analyzers often need to simultaneously check a few dozen or even hundreds
of value-flow properties, causing serious scalability issues when high precision is required …

We describe a thoroughly interweaved forward and backward version of PDR/IC3 called
fbPDR. Motivated by the complementary strengths of PDR and Reverse PDR and by related …

From equivalence checking to functional verification to design-space exploration, industrial
verification tasks entail checking a large number of properties on the same design. State-of …

In this article, we revisit the topic of generalizing proof obligations (POs) in bit-level property
directed reachability (PDR). We provide a comprehensive study which: 1) determines the …

Multi-property verification has emerged as a con-temporary challenge in the chip design
industry. With designs now encompassing hundreds of properties, conventional sequential …

The design of safety-critical systems often requires design space exploration: comparing
several system models that differ in terms of design choices, capabilities, and …

This paper addresses model checking based on SAT solvers and Craig interpolants. We
tackle major scalability problems of state-of-the-art interpolation-based approaches, and we …

This work aims to solve a practical problem, ie, how to quantify the risk brought upon a
system by different attackers. The answer is useful for optimising resource allocation for …

In this work, we study the problem of verification of systems in the presence of attackers
using bounded model checking. Given a system and a set of security requirements, we …