Data and memory optimization techniques for embedded systems
We present a survey of the state-of-the-art techniques used in performing data and memory-
related optimizations in embedded systems. The optimizations are targeted directly or …
related optimizations in embedded systems. The optimizations are targeted directly or …
On-chip vs. off-chip memory: the data partitioning problem in embedded processor-based systems
Efficient utilization of on-chip memory space is extremely important in modern embedded
system applications based on processor cores. In addition to a data cache that interfaces …
system applications based on processor cores. In addition to a data cache that interfaces …
[图书][B] Memory issues in embedded systems-on-chip: optimizations and exploration
Memory Issues in Embedded Systems-On-Chip: Optimizations and Explorations is designed
for different groups in the embedded systems-on-chip arena. First, it is designed for …
for different groups in the embedded systems-on-chip arena. First, it is designed for …
Local memory exploration and optimization in embedded systems
Embedded processor-based systems allow for the tailoring of the on-chip memory
architecture based on application specific requirements. We present an analytical strategy …
architecture based on application specific requirements. We present an analytical strategy …
An algorithm for array variable clustering
L Ramachandran, DD Gajski… - … of European Design …, 1994 - ieeexplore.ieee.org
During synthesis of behavioral descriptions array variables are implemented with memory
modules. In this paper we show that simple one-to-one mapping between the array …
modules. In this paper we show that simple one-to-one mapping between the array …
Synthesis of application-specific memory designs
H Schmit, DE Thomas - IEEE Transactions on Very Large Scale …, 1997 - ieeexplore.ieee.org
This paper discusses the mapping of arrays in a behavior to memories in an implementation.
We introduce a novel approach to the design of memory systems, which is based on a …
We introduce a novel approach to the design of memory systems, which is based on a …
Exploiting off-chip memory access modes in high-level synthesis
Memory-intensive behaviors often contain large arrays that are synthesized into off-chip
memories. With the increasing gap between on-chip and off-chip memory access delays, it is …
memories. With the increasing gap between on-chip and off-chip memory access delays, it is …
Memory design and exploration for low power, embedded systems
WT Shiue, C Chakrabarti - Journal of VLSI signal processing systems for …, 2001 - Springer
In this paper, we describe a procedure for memory design and exploration for low power
embedded systems. Our system consists of an instruction cache and a data cache on-chip …
embedded systems. Our system consists of an instruction cache and a data cache on-chip …
Optimal register assignment to loops for embedded code generation
One of the challenging tasks in code generation for embedded systems is register
assignment. When more live variables than registers exist, some variables will necessarily …
assignment. When more live variables than registers exist, some variables will necessarily …
Compatibility path based binding algorithm for interconnect reduction in high level synthesis
T Kim, X Liu - 2007 IEEE/ACM International Conference on …, 2007 - ieeexplore.ieee.org
This paper describes a register and functional unit (FU) binding al-gorithm in high level
synthesis. Our algorithm targets the reduction of multiplexer inputs. Since multiplexers …
synthesis. Our algorithm targets the reduction of multiplexer inputs. Since multiplexers …