Clock-gating of streaming applications for energy efficient implementations on FPGAs

E Bezati, S Casale-Brunet, M Mattavelli… - … on Computer-Aided …, 2016 - ieeexplore.ieee.org
This paper investigates the reduction of dynamic power for streaming applications yielded
by asynchronous dataflow designs by using clock gating techniques. Streaming applications …

E-Mapper: Energy-Efficient Resource Allocation for Traditional Operating Systems on Heterogeneous Processors

T Smejkal, R Khasanov, J Castrillon… - arXiv preprint arXiv …, 2024 - arxiv.org
Energy efficiency has become a key concern in modern computing. Major processor
vendors now offer heterogeneous architectures that combine powerful cores with energy …

Turnus: a unified dataflow design space exploration framework for heterogeneous parallel systems

S Casale-Brunet, C Alberti, M Mattavelli… - 2013 Conference on …, 2013 - ieeexplore.ieee.org
This paper presents the main features of the TURNUS co-exploration environment, an
unified design space exploration framework suitable for heterogeneous parallel systems …

Automated design flow for multi-functional dataflow-based platforms

C Sau, P Meloni, L Raffo, F Palumbo, E Bezati… - Journal of Signal …, 2016 - Springer
The implementation of processing platforms supporting multiple applications by runtime
reconfigurations on dedicated hardware modules requires the solution of different problems …

Partitioning and optimization of high level stream applications for multi clock domain architectures

SC Brunet, E Bezati, C Alberti, M Mattavelli… - SiPS 2013 …, 2013 - ieeexplore.ieee.org
In this paper we propose a design methodology to partition dataflow applications on a multi
clock domain architecture. This work shows how starting from a high level dataflow …

From dataflow-based video coding tools to dedicated embedded multi-core platforms

H Yviquel - 2013 - theses.hal.science
The development of multimedia technology, along with the emergence of parallel
architectures, has revived the interest on dataflow programming for designing embedded …

[PDF][PDF] High-level synthesis of dataflow programs for heterogeneous platforms: design flow tools and design space exploration

E Bezati - 2015 - infoscience.epfl.ch
The growing complexity of digital signal processing applications implemented in
programmable logic and embedded processors make a compelling case the use of high …

[HTML][HTML] Verifying parallel dataflow transformations with model checking and its application to FPGAs

R Stewart, B Berthomieu, P Garcia, I Ibrahim… - Journal of Systems …, 2019 - Elsevier
Dataflow languages are widely used for programming real-time embedded systems. They
offer high level abstraction above hardware, and are amenable to program analysis and …

Memory Footprint Reduction for Dataflow Process Networks using Virtual Channels

F Krebs, K Schneider - MBMV 2024; 27. Workshop, 2024 - ieeexplore.ieee.org
Synthesizing code from dataflow process networks requires implementing the
communication channels as queues in software. Common approaches use fixed-size …

Multi-clock domain optimization for reconfigurable architectures in high-level dataflow applications

SC Brunet, E Bezati, C Alberti… - … on Signals, Systems …, 2013 - ieeexplore.ieee.org
This paper proposes a new design methodology to partition streaming applications onto a
multi clock domain architecture. The objective is to save power by running different parts of …