A memory-based FFT processor design with generalized efficient conflict-free address schemes
KF Xia, B Wu, T Xiong, TC Ye - IEEE Transactions on Very …, 2017 - ieeexplore.ieee.org
This paper presents the design and implementation of memory-based fast Fourier transform
(FFT) processors with generalized efficient, conflict-free address schemes. We unified the …
(FFT) processors with generalized efficient, conflict-free address schemes. We unified the …
Multimode memory-based FFT processor for wireless display FD-OCT medical systems
SN Tang, FC Jan, HW Cheng, CK Lin… - IEEE Transactions on …, 2014 - ieeexplore.ieee.org
This paper presents a multimode memory-based Fast Fourier Transform (FFT) processor for
a medical system aimed at Fourier-domain optical coherence tomography (FD-OCT) …
a medical system aimed at Fourier-domain optical coherence tomography (FD-OCT) …
[PDF][PDF] Automatic IP generation of FFT/IFFT processors with word-length optimization for MIMO-OFDM systems
PY Tsai, CW Chen, MY Huang - EURASIP Journal on Advances in Signal …, 2011 - Springer
A systematic approach is presented for automatically generating variable-size FFT/IFFT soft
intellectual property (IP) cores for MIMO-OFDM systems. The finite-precision effect in an FFT …
intellectual property (IP) cores for MIMO-OFDM systems. The finite-precision effect in an FFT …
Novel shared multiplier scheduling scheme for area-efficient FFT/IFFT processors
This paper proposes a shared multiplier scheduling scheme (SMSS) for area-efficient fast
Fourier transform (FFT)/inverse FFT processors. SMSS can significantly reduce the total …
Fourier transform (FFT)/inverse FFT processors. SMSS can significantly reduce the total …
A novel addressing algorithm of radix-2 FFT using single-bank dual-port memory
Purpose This paper aims to present a single-block memory-based FFT processor design
with a conflict-free addressing scheme for field-programmable gate arrays FPGAs with dual …
with a conflict-free addressing scheme for field-programmable gate arrays FPGAs with dual …
[PDF][PDF] Reconfigurable FPGA-based baseband processor for multi-mode spectrum aggregation
ML Ferreira - 2019 - repositorio-aberto.up.pt
The fifth generation (5G) of cellular communications will revolutionize the way humans and
machines interact with each other and lead to deep technological, social and economic …
machines interact with each other and lead to deep technological, social and economic …
低功耗無線可攜式多媒體播放器之設計與分析
李宏哲 - 臺北科技大學資訊工程系研究所學位論文, 2008 - airitilibrary.com
嵌入式系統和無線通訊是電子裝置的兩個發展趨勢. 許多消費型電子產品都被設計成行動裝置,
而這類設備最被重視的問題是功率消耗, 因其使用時間與功率消耗息息相關. 近年來 …
而這類設備最被重視的問題是功率消耗, 因其使用時間與功率消耗息息相關. 近年來 …
Efficient memory management scheme for pipelined shared-memory FFT processors
HF Luo, MD Shieh - 2015 IEEE International Conference on …, 2015 - ieeexplore.ieee.org
This paper presents an efficient memory management scheme for pipelined shared-memory
architectures of the fast Fourier transform (FFT). A multi-path delay commutator (MDC) with a …
architectures of the fast Fourier transform (FFT). A multi-path delay commutator (MDC) with a …
The Design and Implementation of High Speed Hybrid Radices Reconfigurable FFT Processor
Q Yuan, H Zhang, Y Song, C Li, X Liu… - 2019 IEEE 13th …, 2019 - ieeexplore.ieee.org
In this paper, a new hybrid radices reconfigurable FFT processor is proposed, which
supports computing modes of radixes 2/4/8 and their combination, satisfying 2 n (n= 6, 7 …
supports computing modes of radixes 2/4/8 and their combination, satisfying 2 n (n= 6, 7 …
[PDF][PDF] Power Efficient FFT Architecture using SMSS for High Speed Real Time Application
KP ANUPRIYA, MK RACHANA - 2017 - ijvdcs.org
This paper consist of an implementation of shared multiplier scheduling scheme on radix-2
FFT architecture for High speed real time application. It is an area efficient architecture. In …
FFT architecture for High speed real time application. It is an area efficient architecture. In …