Computer Architecture: A Quantitative Approach, Fifth Edition, explores the ways that
software and technology in the cloud are accessed by digital media, such as cell phones …

Today's high performance processors tolerate long latency operations by means of out-of-
order execution. However, as latencies increase, the size of the instruction window must …

For maximum performance, an out-of-order processor must issue load instructions as early
as possible, while avoiding memory-order violations with prior store instructions that write to …

Computer architects employ a series of performance optimizations at the micro-architecture
level. These optimizations are meant to be invisible to the programmer but they are implicitly …

We introduce a dynamic scheme that captures the accesspat-terns of linked data structures
and can be used to predict future accesses with high accuracy. Our technique exploits the …

Mispredicted branches and loads that miss in the cache cause the majority of retirement
stalls experienced by sequential processors; we call these critical instructions. Despite their …

We propose methods for reducing the energy consumed by snoop requests in snoopy bus-
based symmetric multiprocessor (SMP) systems. Observing that a large fraction of snoops …

Despite the success of instruction-level parallelism (ILP) optimizations in increasing the
performance of microprocessors, certain codes remain elusive. In particular, codes …

State of the art microprocessors achieve high performance by executing multiple instructions
per cycle. In an out-of-order engine, the instruction scheduler is responsible for dispatching …

CPU cache is a limited but crucial storage component in modern processors, whereas the
cache timing side-channel may inadvertently leak information through the physically …