The evergrowing memory demand fueled by datacenter workloads is the driving force
behind new memory technology innovations (eg, NVM, CXL). Tiered memory is a promising …

Address translation is a performance bottleneck in data-intensive workloads due to large
datasets and irregular access patterns that lead to frequent high-latency page table walks …

Tiered memory systems introduce an additional memory level with higher-than-local-DRAM
access latency and require sophisticated memory management mechanisms to achieve cost …

We propose a new framework called CachedArrays and a set of APIs to address the data
tiering problem in large scale heterogeneous and disaggregated memory systems. The …

Conventional virtual memory (VM) frameworks enable a virtual address to flexibly map to
any physical address. This flexibility necessitates large data structures to store virtual-to …

Data-hungry applications that require terabytes of memory have become widespread in
recent years. To meet the memory needs of these applications, data centers are embracing …

As the memory footprint of emerging applications continues to increase, the address
translation becomes a critical performance bottleneck owing to frequent misses on the …

High-performance computing (HPC) workloads such as scientific simulations and deep
learning (DL) running across multi-GPU systems are memory and data-intensive, relying on …

Constructing tiered memory systems becomes prevalent in cloud and datacenter servers
due to its benefits on large capacity and low total cost of ownership. Since such tiered …

Non-Volatile Memory (NVM) can deliver higher density and lower cost per bit when
compared with DRAM. Its main drawback is that it is slower than DRAM. On the other hand …