Constraint-based automatic SBST generation for RISC-V processor families
T Faller, NI Deligiannis, M Schwörer… - 2023 IEEE European …, 2023 - ieeexplore.ieee.org
Software-Based Self-Tests (SBST) allow at-speed, native online-testing of processors by
running software programs on the processor core, requiring no Design for Testability (DfT) …
running software programs on the processor core, requiring no Design for Testability (DfT) …
Self-test library generation for in-field test of path delay faults
New semiconductor technologies for advanced applications are more prone to defects and
imperfections related, among several different causes, to the manufacturing process, aging …
imperfections related, among several different causes, to the manufacturing process, aging …
Assessing the Effectiveness of Software-Based Self-Test Programs for Static Cell-Aware Test
Software-Based Self-Test (SBST) is vastly adopted as a hardware safety mechanism for the
in-field test of safety-critical systems in the form of Software Test Libraries (STLs). Typically …
in-field test of safety-critical systems in the form of Software Test Libraries (STLs). Typically …
Special Session: Software-Based Self-Test Generation for RISC-V–Stuck-At Generation, Functional Cell-Aware Untestability, and FPGA Demonstration–
Software-Based Self-Tests (SBST) allow at-speed, native online-testing of processors by
running software programs on the processor core, requiring no Design for Testability (DfT) …
running software programs on the processor core, requiring no Design for Testability (DfT) …
[PDF][PDF] Formal Methods for Test and Reliability
N Deligiannis - 2024 - tesidottorato.depositolegale.it
In the rapidly evolving landscape of nanotechnology, where innovations promise
groundbreaking advancements in various industries, ensuring the reliability and safety of …
groundbreaking advancements in various industries, ensuring the reliability and safety of …
A 6-bit Low-Area Hybrid ADC Design For System-on-Chip Measurements
N Kolahimahmoudi, G Insinga, S Roggi… - … on Design, Test and …, 2024 - ieeexplore.ieee.org
In recent years, with the declining dimensions of transistors, the system-on-chips (SoCs)
have had more physical defects. These physical defects ultimately result in failures that …
have had more physical defects. These physical defects ultimately result in failures that …
Soluzioni di test funzionali per delay faults nelle CPU
N Kolahimahmoudi - 2022 - webthesis.biblio.polito.it
Il lavoro di tesi presentato si concentra sul test funzionale per i guasti di ritardo e indaga per
possibili soluzioni. Per eseguire test funzionali su circuiti integrati, le librerie di autotest …
possibili soluzioni. Per eseguire test funzionali su circuiti integrati, le librerie di autotest …
[PDF][PDF] New Techniques to Detect and Mitigate Aging Effects in Advanced Semiconductor Technologies
S Sartoni - 2023 - tesidottorato.depositolegale.it
New advanced semiconductor technologies are increasingly adopted in emerging
applications, as they provide high computational capabilities together with reduced power …
applications, as they provide high computational capabilities together with reduced power …
[PDF][PDF] Self-Test Libraries for RISC-V safety-critical applications: recent advances
RISC-V adoption is rapidly expanding even to safety-critical application areas, such as
automotive, space, robotics, and health-care. In these areas, it is crucial to guarantee that …
automotive, space, robotics, and health-care. In these areas, it is crucial to guarantee that …
New techniques to detect and mitigate aging effects in advanced semiconductor technologies
Advanced semiconductor technologies present more frequent physical defects and a shorter
lifespan. Some of these defects cannot be tested by means of traditional fault models, as …
lifespan. Some of these defects cannot be tested by means of traditional fault models, as …