This article presents a millimeter-wave (mmW) frequency synthesizer based on a new charge-sharing locking (CSL) technique. A charge-preset capacitor is introduced for charge …
T Xu, S Zhong, J Yin, PI Mak… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
This paper presents a type-II reference-sampling (RS) phase-locked loop (PLL) exploiting a novel gain-boosting reference-sampling phase detector (RSPD) to reduce the in-band …
We introduce a new mode of oscillation in an LC-tank: an inverse class-F 23. In contrast to the conventional class-F oscillators, in which a high value of the real impedance (ie …
J Du, T Siriburanon, Y Hu, V Govindaraj… - IEEE Journal of Solid …, 2021 - ieeexplore.ieee.org
This article presents a low-power fractional-all-digital phase-locked loop (ADPLL) employing a reference-waveform oversampling (ROS) phase detector (PD) that increases its effective …
This letter proposes a mm-wave fractional-N reference-oversampling (ROS) all-digital phase- locked loop (ADPLL) for 5G wireless applications utilizing a relatively low but standard …
This article presents a wide-band suppression technique of flicker phase noise (PN) by means of a gate–drain phase shift in a transformer-based complementary oscillator. We …
Y Hu, W Tao, RB Staszewski - IEEE Open Journal of the Solid …, 2024 - ieeexplore.ieee.org
A fractional-N frequency synthesizer with low total jitter [eg,< 50fsrms, accounting for both phase noise (PN) and spurs] is essential for enabling the emerging 5G/6G and other high …
GM Sung, CC Huang, X Xiao, SY Hsu - Electronics, 2022 - mdpi.com
In this paper, we present a successive approximation register (SAR) analog-to-digital converter (ADC) with a charge-pump (CP) phase-locked loop (PLL) and a bootstrapped …
T Siriburanon, C Liu, J Du… - IEEE Open Journal of …, 2024 - ieeexplore.ieee.org
This article proposes an mm-wave fractional-N all-digital phase-locked loop (ADPLL) employing a reference-waveform oversampling (ROS) phase detector (PD) that increases its …