Oscillator flicker phase noise: A tutorial

Y Hu, T Siriburanon… - IEEE Transactions on …, 2020 - ieeexplore.ieee.org
A deep understanding of how to reduce flicker phase noise (PN) in oscillators is critical in
supporting ultra-low PN frequency generation for the advanced communications and other …

A charge-sharing locking technique with a general phase noise theory of injection locking

Y Hu, X Chen, T Siriburanon, J Du… - IEEE Journal of Solid …, 2021 - ieeexplore.ieee.org
This article presents a millimeter-wave (mmW) frequency synthesizer based on a new
charge-sharing locking (CSL) technique. A charge-preset capacitor is introduced for charge …

A 6-to-7.5-GHz 54-fsrms Jitter Type-II Reference-Sampling PLL Featuring a Gain-Boosting Phase Detector for In-Band Phase-Noise Reduction

T Xu, S Zhong, J Yin, PI Mak… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
This paper presents a type-II reference-sampling (RS) phase-locked loop (PLL) exploiting a
novel gain-boosting reference-sampling phase detector (RSPD) to reduce the in-band …

A Compact 0.2–0.3-V Inverse-Class-F23 Oscillator for Low 1/f3 Noise Over Wide Tuning Range

J Du, Y Hu, T Siriburanon, E Kobal… - IEEE Journal of Solid …, 2021 - ieeexplore.ieee.org
We introduce a new mode of oscillation in an LC-tank: an inverse class-F 23. In contrast to
the conventional class-F oscillators, in which a high value of the real impedance (ie …

A reference-waveform oversampling technique in a fractional-N ADPLL

J Du, T Siriburanon, Y Hu, V Govindaraj… - IEEE Journal of Solid …, 2021 - ieeexplore.ieee.org
This article presents a low-power fractional-all-digital phase-locked loop (ADPLL) employing
a reference-waveform oversampling (ROS) phase detector (PD) that increases its effective …

A Millimeter-Wave ADPLL With Reference Oversampling and Third-Harmonic Extraction Featuring High FoMjitter-N

J Du, T Siriburanon, X Chen, Y Hu… - IEEE Solid-State …, 2021 - ieeexplore.ieee.org
This letter proposes a mm-wave fractional-N reference-oversampling (ROS) all-digital phase-
locked loop (ADPLL) for 5G wireless applications utilizing a relatively low but standard …

Flicker phase-noise reduction using gate–drain phase shift in transformer-based oscillators

X Chen, Y Hu, T Siriburanon, J Du… - … on Circuits and …, 2021 - ieeexplore.ieee.org
This article presents a wide-band suppression technique of flicker phase noise (PN) by
means of a gate–drain phase shift in a transformer-based complementary oscillator. We …

Nonlinearity-Induced Spur Analysis in Fractional-N Synthesizers With ΔΣ Quantization Cancellation

Y Hu, W Tao, RB Staszewski - IEEE Open Journal of the Solid …, 2024 - ieeexplore.ieee.org
A fractional-N frequency synthesizer with low total jitter [eg,< 50fsrms, accounting for both
phase noise (PN) and spurs] is essential for enabling the emerging 5G/6G and other high …

10-Bit 5 MS/s Successive Approximation Register Analog-to-Digital Converter with a Phase-Locked Loop and Modified Bootstrapped Switch for a BLDC Motor Drive

GM Sung, CC Huang, X Xiao, SY Hsu - Electronics, 2022 - mdpi.com
In this paper, we present a successive approximation register (SAR) analog-to-digital
converter (ADC) with a charge-pump (CP) phase-locked loop (PLL) and a bootstrapped …

Millimeter-Wave All-Digital Phase-Locked Loop Using Reference Waveform Oversampling Techniques

T Siriburanon, C Liu, J Du… - IEEE Open Journal of …, 2024 - ieeexplore.ieee.org
This article proposes an mm-wave fractional-N all-digital phase-locked loop (ADPLL)
employing a reference-waveform oversampling (ROS) phase detector (PD) that increases its …