SPACX: Silicon photonics-based scalable chiplet accelerator for DNN inference

Y Li, A Louri, A Karanth - 2022 IEEE International Symposium …, 2022 - ieeexplore.ieee.org
In pursuit of higher inference accuracy, deep neural network (DNN) models have
significantly increased in complexity and size. To overcome the consequent computational …

SPRINT: A high-performance, energy-efficient, and scalable chiplet-based accelerator with photonic interconnects for CNN inference

Y Li, A Louri, A Karanth - IEEE Transactions on Parallel and …, 2021 - ieeexplore.ieee.org
Chiplet-based convolution neural network (CNN) accelerators have emerged as a promising
solution to provide substantial processing power and on-chip memory capacity for CNN …

Ascend: A scalable and energy-efficient deep neural network accelerator with photonic interconnects

Y Li, K Wang, H Zheng, A Louri… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
The complexity and size of recent deep neural network (DNN) models have increased
significantly in pursuit of high inference accuracy. Chiplet-based accelerator is considered a …

Scaling deep-learning inference with chiplet-based architecture and photonic interconnects

Y Li, A Louri, A Karanth - 2021 58th ACM/IEEE Design …, 2021 - ieeexplore.ieee.org
Chiplet-based architectures have been proposed to scale computing systems for deep
neural networks (DNNs). Prior work has shown that for the chiplet-based DNN accelerators …

PROWAVES: Proactive runtime wavelength selection for energy-efficient photonic NoCs

A Narayan, Y Thonnart, P Vivet… - IEEE Transactions on …, 2020 - ieeexplore.ieee.org
2.5-D manycore systems running parallel applications are severely bottlenecked by network-
on-chip (NoC) latencies and bandwidth. Traditionally, NoCs are composed of electrical links …

ReSiPI: A reconfigurable silicon-photonic 2.5 D chiplet network with PCMs for energy-efficient interposer communication

E Taheri, S Pasricha, M Nikdast - Proceedings of the 41st IEEE/ACM …, 2022 - dl.acm.org
2.5 D chiplet systems have been proposed to improve the low manufacturing yield of large-
scale chips. However, connecting the chiplets through an electronic interposer imposes a …

Design of reconfigurable on-chip wireless interconnections through optical phased arrays

G Calò, G Bellanca, M Barbiroli, F Fuschini… - Optics …, 2021 - opg.optica.org
In this paper we report the design of a device allowing on-chip optical wireless
interconnections, based on transmitting and receiving Optical Phased Arrays (OPA). The …

The Survey of Chiplet-based Integrated Architecture: An EDA perspective

S Chen, H Zhang, Z Ling, J Zhai, B Yu - arXiv preprint arXiv:2411.04410, 2024 - arxiv.org
Enhancing performance while reducing costs is the fundamental design philosophy of
integrated circuits (ICs). With advancements in packaging technology, interposer-based …

Architecting optically controlled phase change memory

A Narayan, Y Thonnart, P Vivet, A Coskun… - ACM Transactions on …, 2022 - dl.acm.org
Phase Change Memory (PCM) is an attractive candidate for main memory, as it offers non-
volatility and zero leakage power while providing higher cell densities, longer data retention …

Polarization effect on the performance of on-chip wireless optical point-to-point links

G Calò, G Bellanca, F Fuschini, M Barbiroli, V Tralli… - Applied Sciences, 2023 - mdpi.com
Optical on-chip wireless interconnection is an emerging technology that aims to overcome
the communication bottleneck in computing architectures and in which multiple processing …