Efficient simulation of formal processor models
M Wilding, D Greve, D Hardin - Formal Methods in System Design, 2001 - Springer
Computer systems under development are routinely modeled by simulators, and formal
verification can be integrated into conventional computer system development by reasoning …
verification can be integrated into conventional computer system development by reasoning …
Transforming the theorem prover into a digital design tool: From concept car to off-road vehicle
D Hardin, M Wilding, D Greve - … , CAV'98 Vancouver, BC, Canada, June 28 …, 1998 - Springer
As digital designs grow evermore complex and design cycles become ever shorter,
traditional informal methods of design verification are proving inadequate. Design teams are …
traditional informal methods of design verification are proving inadequate. Design teams are …
[HTML][HTML] Modeling and verification of real-time software using extended linear hybrid automata
S Vestal - NASA CONFERENCE PUBLICATION, 2000 - books.google.com
Linear hybrid automata are finite state automata augmented with real-valued variables.
Transitions between discrete states may be conditional on the values of these variables and …
Transitions between discrete states may be conditional on the values of these variables and …
ACL2 support for verification projects
M Kaufmann - International Conference on Automated Deduction, 1998 - Springer
ACL2 support for verification projects Page 1 Invited TalkACL2 Support for Verification Projects
Matt Kaufmann EDS CIO Services 98 San Jacinto Blvd., Suite 500 Austin, TX 78701, USA …
Matt Kaufmann EDS CIO Services 98 San Jacinto Blvd., Suite 500 Austin, TX 78701, USA …
A two-level approach to automated conformance testing of VHDL designs
J Moonen, J Romijn, O Sies, J Springintveld… - … Systems: IFIP TC6 10th …, 1997 - Springer
For manufacturers of consumer electronics, conformance testing of embedded software is a
vital issue. To improve performance, parts of this software are implemented in hardware …
vital issue. To improve performance, parts of this software are implemented in hardware …
Formal methods technology transfer: A view from NASA
JL Caldwell - Formal Methods in System Design, 1998 - Springer
Abstract Since 1988 NASA Langley Research Center has supported a formal methods
research program. From its inception, a primary goal of the program has been to transfer …
research program. From its inception, a primary goal of the program has been to transfer …
[图书][B] Formal semantics and proof techniques for optimizing VHDL models
K Umamageswaran, SL Pandey, PA Wilsey - 1999 - books.google.com
Formal Semantics and Proof Techniques for Optimizing VHDL Models presents a formal
model of VHDL that clearly specifies both the static and dynamic semantics of VHDL. It …
model of VHDL that clearly specifies both the static and dynamic semantics of VHDL. It …
Formal specification in VHDL for hardware verification
R Reetz, K Schneider, T Kropf - … Design, Automation and Test …, 1998 - ieeexplore.ieee.org
In this paper, we enrich VHDL with new specification constructs intended for hardware
verification. Using our extensions, total correctness properties may now be stated whereas …
verification. Using our extensions, total correctness properties may now be stated whereas …
Deadlock detection in FPGA design: A practical approach
D Wang, F He, Y Deng, C Su, M Gu… - Tsinghua Science and …, 2015 - ieeexplore.ieee.org
Formal verification of VHSIC Hardware Description Language (VHDL) in Field-
Programmable Gate Array (FPGA) design has been discussed for many years. In this paper …
Programmable Gate Array (FPGA) design has been discussed for many years. In this paper …
[图书][B] Bayesian based stopping rules for behavioral VHDL verification
AFA Hajjar - 2001 - search.proquest.com
Verification of complex behavioral models has become a critical and time-consuming
process in hardware design. During behavioral model verification, it is important to …
process in hardware design. During behavioral model verification, it is important to …