A parallelizing compiler cooperative heterogeneous multicore processor architecture
Heterogeneous multicore architectures, integrating several kinds of accelerator cores in
addition to general purpose processor cores, have been attracting much attention to realize …
addition to general purpose processor cores, have been attracting much attention to realize …
Hot-swapping architecture extension for mitigation of permanent functional unit faults
ZE Rakosi, M Hiromoto, H Ochi… - … Conference on Field …, 2009 - ieeexplore.ieee.org
Due to latest advances in semiconductor integration, systems are becoming more
susceptible to faults leading to temporary or permanent failures. We propose a new …
susceptible to faults leading to temporary or permanent failures. We propose a new …
Power-efficient heteregoneous parallelism for digital convergence
K Uchiyama - 2008 IEEE Symposium on VLSI Circuits, 2008 - ieeexplore.ieee.org
For embedded systems in the digital-convergence era, various functions such as
communication, security, audio, video, and recognition, are required in a single device …
communication, security, audio, video, and recognition, are required in a single device …
Low Power Multicore Processors for Embedded Systems
F Arakawa - Embedded Systems: Hardware, Design, and …, 2012 - Wiley Online Library
A multicore chip is one of the most promising approaches to achieve high performance.
Formerly, frequency scaling was the best approach. However, the scaling has hit the power …
Formerly, frequency scaling was the best approach. However, the scaling has hit the power …
Chip Implementations
K Uchiyama, F Arakawa, H Kasahara, T Nojiri… - … for Embedded Systems, 2012 - Springer
Three prototype multicore chips, RP-1, RP-2, and RP-X, were implemented with the highly
efficient cores described in Chap. 3. The details of the chips are described in this chapter …
efficient cores described in Chap. 3. The details of the chips are described in this chapter …
A 45-nm 37.3 GOPS/W heterogeneous multi-core SOC with 16/32 bit instruction-set general-purpose core
O Nishii, Y Yuyama, M Ito, Y Kiyoshige… - IEICE transactions on …, 2011 - search.ieice.org
We built a 12.4 mm< cd0215f. gif> 12.4 mm, 45-nm CMOS, chip that integrates eight 648-
MHz general purpose cores, two matrix processor (MX-2) cores, four flexible engine (FE) …
MHz general purpose cores, two matrix processor (MX-2) cores, four flexible engine (FE) …
Multi-Core/Multi-IP Technology for Embedded Applications
N Irie, T Hattori - IEICE transactions on electronics, 2009 - search.ieice.org
SoC has driven the evolution of embedded systems or consumer electronics. Multi-
core/multi-IP is the key technology to integrate many functions on a SoC for future …
core/multi-IP is the key technology to integrate many functions on a SoC for future …
ヘテロジニアスマルチコアプロセッサ上でのスタティックスケジューリングを用いたMP3 エンコーダの並列化
和田康孝， 林明宏， 益浦健， 白子準… - 情報処理学会論文誌 …, 2008 - ipsj.ixsq.nii.ac.jp
論文抄録 情報家電の市場拡大にともない, 低消費電力でありながら高い性能を実現するプロセッサ
が求められるようになっている. この要求に対応するため, 汎用プロセッサに加え, 動的再構成可能 …
が求められるようになっている. この要求に対応するため, 汎用プロセッサに加え, 動的再構成可能 …