Bounded satisfiability checking of metric temporal logic specifications

M Pradella, A Morzenti, PS Pietro - ACM Transactions on Software …, 2013 - dl.acm.org
We introduce bounded satisfiability checking, a verification technique that extends bounded
model checking by allowing also the analysis of a descriptive model, consisting of temporal …

Safety monitor for train‐centric CBTC system

H Wang, N Zhao, B Ning, T Tang… - IET Intelligent Transport …, 2018 - Wiley Online Library
Train‐centric communications‐based train control (TcCBTC) system is a new solution for
urban transit signalling. Compared to traditional train control systems, the on‐board …

Towards Quantum Requirements Engineering

P Spoletini - 2023 IEEE 31st International Requirements …, 2023 - ieeexplore.ieee.org
Quantum computing is rapidly transitioning from a scientific curiosity to an industrial reality,
offering the potential to overcome classical computation limitations. This shift has given rise …

The symmetry of the past and of the future: bi-infinite time in the verification of temporal properties

M Pradella, A Morzenti, P San Pietro - Proceedings of the the 6th joint …, 2007 - dl.acm.org
Model checking techniques have traditionally dealt with temporal logic languages and
automata interpreted over ω-words, ie, infinite in the future but finite in the past. However …

[PDF][PDF] Practical model checking of LTL with past

M Pradella, P San Pietro, P Spoletini… - … : 1st Workshop on …, 2003 - pradella.faculty.polimi.it
ABSTRACT LTL (Linear Temporal Logic) has become the standard language for linear-time
model checking. LTL has only future operators, while it is widely accepted that many …

Refining real-time system specifications through bounded model-and satisfiability-checking

M Pradella, A Morzenti… - 2008 23rd IEEE/ACM …, 2008 - ieeexplore.ieee.org
In bounded model checking (BMC) a system is modeled with a finite automaton and various
desired properties with temporal logic formulae. Property verification is achieved by …

[PDF][PDF] RC interconnect synthesis—a moment fitting approach

N Menezes, S Pullela, F Dartu… - Proceedings of the 1994 …, 1994 - websrv.cecs.uci.edu
Presently, delays due to the physical interconnect between logic gates account for large
portions of the overall path delays. For this reason, synthesis of the logic gate fanout …

Integrating discrete-and continuous-time metric temporal logics through sampling

CA Furia, M Rossi - Formal Modeling and Analysis of Timed Systems: 4th …, 2006 - Springer
Real-time systems usually encompass parts that are best described by a continuous-time
model, such as physical processes under control, together with other components that are …

Trio2Promela: A model checker for temporal metric specifications

D Bianculli, A Morzenti, M Pradella… - … (ICSE'07 Companion …, 2007 - ieeexplore.ieee.org
We present Trio2Promela, a tool for model checking metric temporal logic specifications
written in the TRIO language. Our approach is based on the translation of formulae into …

Model checking temporal metric specifications with Trio2Promela

D Bianculli, P Spoletini, A Morzenti, M Pradella… - … on Fundamentals of …, 2007 - Springer
Abstract We present Trio2Promela, a tool for model checking TRIO specifications by means
of Spin. TRIO is a linear-time temporal logic with both future and past operators and a …