Rapid thermal processing apparatus for processing semiconductor wafers
GM Moore, K Nishikawa - US Patent 5,444,217, 1995 - Google Patents
4,497,683 2/1985 Celler et al...... 156/603 ceptor position control rotates the wafers during
pro 4,511,788 4/1985 Arai et al...... 219/405 cessing and raises and lowers the susceptor to …
pro 4,511,788 4/1985 Arai et al...... 219/405 cessing and raises and lowers the susceptor to …
Selective deposition of amorphous and polycrystalline silicon
HM Liaw, CA Seelbach - US Patent 4,963,506, 1990 - Google Patents
A method for selectively depositing amorphous or polycrystalline silicon wherein a wafer
having exposed silicon regions thereon is placed into a CVD reactor and subjected to a …
having exposed silicon regions thereon is placed into a CVD reactor and subjected to a …
Structure and method of a strained channel transistor and a second semiconductor component in an integrated circuit
(57) ABSTRACT A semiconductor chip includes a semiconductor Substrate 126, in which
first and second active regions are disposed. A resistor 124 is formed in the first active …
first and second active regions are disposed. A resistor 124 is formed in the first active …
Strained channel complementary field-effect transistors
US PATENT DOCUMENTS formed from a first semiconductor material and the Source
4,069,094. A 1, 1978 Sh 1 and drain regions are formed from a second semiconductor 43 1 …
4,069,094. A 1, 1978 Sh 1 and drain regions are formed from a second semiconductor 43 1 …
Rapid thermal processing apparatus for processing semiconductor wafers
GM Moore, K Nishikawa - US Patent 5,683,518, 1997 - Google Patents
4 101 759 7/1978 Anthony et a] 219,343 chamber. Instead of the second heat source, a
passive heat 41113347 9/1978 Km 6, a1 '' 156/612 distribution element is used, in one …
passive heat 41113347 9/1978 Km 6, a1 '' 156/612 distribution element is used, in one …
Semiconductor devices having strained dual channel layers
MT Currie, AJ Lochtefeld, CW Leitz… - US Patent …, 2006 - Google Patents
A semiconductor structure includes a strain-inducing substrate layer having a germanium
concentration of at least 10 atomic%. The semiconductor structure also includes a …
concentration of at least 10 atomic%. The semiconductor structure also includes a …
Semiconductor diode with reduced leakage
BACKGROUND 0002 Transistor size reduction has resulted in the thin ning of insulator
layerS Such as the gate dielectric. These thinner dielectric layerS fail at lower Voltages …
layerS Such as the gate dielectric. These thinner dielectric layerS fail at lower Voltages …
Laser annealing method for a semiconductor thin film
S Maegawa, T Kawamura, M Furuta… - US Patent 5,591,668, 1997 - Google Patents
A laser annealing method for a semiconductor thin film for irradiating the semiconductor thin
film with a laser beam having a section whose outline includes a straight-line portion, so as …
film with a laser beam having a section whose outline includes a straight-line portion, so as …
Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors
In accordance with a preferred embodiment of the present invention, a silicon-on-insulator
(SOI) chip includes a sili con layer of a predetermined thickness overlying an insu lator layer …
(SOI) chip includes a sili con layer of a predetermined thickness overlying an insu lator layer …
Strained channel on insulator device
A semiconductor device 10 includes a substrate 12 (eg, a silicon substrate) with an
insulating layer 14 (eg, an oxide such as silicon dioxide) disposed thereon. A first …
insulating layer 14 (eg, an oxide such as silicon dioxide) disposed thereon. A first …