Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
DE Grupp, DJ Connelly - US Patent 7,176,483, 2007 - Google Patents
An electrical junction that includes a semiconductor (eg, C, Ge, or an Si-based
semiconductor), a conductor, and an interface layer disposed therebetween. The interface …
semiconductor), a conductor, and an interface layer disposed therebetween. The interface …
Process for fabricating a self-aligned deposited source/drain insulated gate field-effect transistor
DE Grupp, DJ Connelly, PA Clifton… - US Patent …, 2011 - Google Patents
Processes for forming self-aligned, deposited Source/drain, insulated gate, transistors and,
in particular, FETs. By depos iting a source/drain in a recess such that it remains only in the …
in particular, FETs. By depos iting a source/drain in a recess such that it remains only in the …
Insulated gate field effect transistor having passivated schottky barriers to the channel
DE Grupp, DJ Connelly - US Patent 7,883,980, 2011 - Google Patents
A transistor includes a semiconductor channel disposed nearby a gate and in an electrical
path between a source and a drain, wherein the channel and at least one of the source or …
path between a source and a drain, wherein the channel and at least one of the source or …
Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
DE Grupp, DJ Connelly - US Patent 8,431,469, 2013 - Google Patents
An electrical device in which an interface layer is disposed between and in contact with a
metal and a Si-based semiconductor, the interface layer being of a thickness effective to …
metal and a Si-based semiconductor, the interface layer being of a thickness effective to …
Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
DE Grupp, DJ Connelly - US Patent 7,884,003, 2011 - Google Patents
US7884003B2 - Method for depinning the fermi level of a semiconductor at an electrical
junction and devices incorporating such junctions - Google Patents US7884003B2 - Method for …
junction and devices incorporating such junctions - Google Patents US7884003B2 - Method for …
Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
DE Grupp, DJ Connelly - US Patent 7,462,860, 2008 - Google Patents
3,983,264 A 9, 1976 Schroen et al. 4,056,642 A 11, 1977 Saxena et al. 4,300,152 A 1
1/1981 Lepselter 4.485, 550 A 12, 1984 Koeneke et al. 5,021,365 A 6, 1991 Kirchner et al …
1/1981 Lepselter 4.485, 550 A 12, 1984 Koeneke et al. 5,021,365 A 6, 1991 Kirchner et al …
Insulated gate field effect transistor having passivated schottky barriers to the channel
DE Grupp, DJ Connelly - US Patent 8,916,437, 2014 - Google Patents
A transistor having at least one passivated Schottky barrier to a channel includes an
insulated gate structure on a p-type substrate in which the channel is located beneath the …
insulated gate structure on a p-type substrate in which the channel is located beneath the …
Process for fabricating a self-aligned deposited source/drain insulated gate field-effect transistor
DE Grupp, DJ Connelly, PA Clifton… - US Patent …, 2012 - Google Patents
US 2011 FO12417OA1 May 26, 2011(74) Attorney, Agent, or Firm—Tarek N. Fahmi, APC
Related US Application Data(57) ABSTRACT (60) Division of application No. 1 1/166,286 …
Related US Application Data(57) ABSTRACT (60) Division of application No. 1 1/166,286 …
Insulated gate field effect transistor having passivated schottky barriers to the channel
DE Grupp, DJ Connelly - US Patent 8,377,767, 2013 - Google Patents
Related US Application Data Continuation of application No. 1 1/403,185, filed on Apr. 11,
2006, now Pat. No. 7,883,980, which is a continuation of application No. 10/754,966, filed on …
2006, now Pat. No. 7,883,980, which is a continuation of application No. 10/754,966, filed on …
Low resistive tungsten dual polymetal gate process for high speed and high density memory devices
We developed ultra-low resistive tungsten dual polymetal gate memory device by using Ti-
based diffusion barrier and a unique tungsten chemical vapor deposition (CVD) process …
based diffusion barrier and a unique tungsten chemical vapor deposition (CVD) process …