Rapid progress in the CMOS technology for the past 25 years has increased the
vulnerability of processors towards faults. Subsequently, focus of computer architects shifted …

Today more than ever before, academia, manufacturers, and hyperscalers acknowledge the
major challenge of silent data corruptions (SDCs) and aim on solutions to minimize its …

Chip manufacturers and hyperscalers are becoming increasingly aware of the problem
posed by Silent Data Errors (SDE) and are taking steps to address it. Major computing …

In this paper, we present gem5-MARVEL, the first consolidated microarchitecture-level fault
injection infrastructure for heterogeneous System-on-Chip architectures comprising CPUs of …

Silent Data Corruptions (SDCs) pose a significant threat to the integrity of digital systems.
These stealthy saboteurs silently corrupt data, remaining undetected by traditional error …

Motion planning is a computationally intensive and well-studied problem in autonomous
robots. However, motion planning hardware accelerators (MPA) must be soft-error resilient …

Silent data corruptions (SDCs) pose a significant challenge to the reliable operation of
modern microprocessors. As the need for enhanced performance and reliability continues to …

This special session paper introduces the Horizon Europe NEUROPULS project, which
targets the development of secure and energy-efficient RISC-V interfaced neuromorphic …

As Neural Processing Units (NPU) or accelerators are increasingly deployed in a variety of
applications including safety critical applications such as autonomous vehicle, and medical …

Instruction-level error injection analyses aim to find instructions where errors often lead to
unacceptable outcomes like Silent Data Corruptions (SDCs). These analyses require …