Power optimization has become a major concern for most digital hardware designers,
particularly in early design phases and especially in limited power budget systems (battery …

With the prevalence of System-on-Chips there is a growing need for automation and
acceleration of the design process. A classical approach is to take a C/C++ specification of …

This book is based on my dissertation. Thus, it presents my work in the area of power
estimation at Electronic System Level as a research assistant of Professor Leupers at the …

The optimization for hardware processor and system for performing deep learning
operations such as Convolutional Neural Networks (CNN) in resource limited embedded …

Many techniques and tools exist to estimate the power consumption and the temperature
map of a chip. These tools help the hardware designers develop power efficient chips in the …

Due to the ever-increasing demands on energy efficiency, designers are struggling to
construct efficient and correct power management strategies for complex System-on-Chips …

Since power is the key aspect in modern systems on chips, many power-reduction
techniques are adopted in the design process, mostly applied through power management …

Today's electronic devices imply significant efforts in pre-silicon low-power design. Key
techniques such as scaling of operating points, or switching power off to unused blocks play …

The increasing complexity of current day Systems-on-Chip and the rising market demands
for low power devices has necessitated the need to perform power analysis of the complete …

This paper describes an early power estimation method for Electronic System Level (ESL)
design, which provides a scalable API to support automated power profiling and analysis at …