[图书][B] VLSI test principles and architectures: design for testability
This book is a comprehensive guide to new DFT methods that will show the readers how to
design a testable and quality product, drive down test cost, improve product quality and …
design a testable and quality product, drive down test cost, improve product quality and …
High performance graph convolutional networks with applications in testability analysis
Applications of deep learning to electronic design automation (EDA) have recently begun to
emerge, although they have mainly been limited to processing of regular structured data …
emerge, although they have mainly been limited to processing of regular structured data …
[图书][B] System-on-chip test architectures: nanometer design for testability
LT Wang, CE Stroud, NA Touba - 2010 - books.google.com
Modern electronics testing has a legacy of more than 40 years. The introduction of new
technologies, especially nanometer technologies with 90nm or smaller geometry, has …
technologies, especially nanometer technologies with 90nm or smaller geometry, has …
Altering a pseudo-random bit sequence for scan-based BIST
NA Touba, EJ McCluskey - Proceedings International Test …, 1996 - ieeexplore.ieee.org
This paper presents a low-overhead scheme for the built-in self-test (BIST) of circuits with
scan. Complete (100%) fault coverage is obtained without modifying the function logic and …
scan. Complete (100%) fault coverage is obtained without modifying the function logic and …
[图书][B] Arithmetic built-in self-test for embedded systems
J Rajski, J Tyszer - 1998 - dl.acm.org
Arithmetic built-in self-test for embedded systems | Guide books skip to main content ACM
Digital Library home ACM home Google, Inc. (search) Advanced Search Browse About Sign …
Digital Library home ACM home Google, Inc. (search) Advanced Search Browse About Sign …
Reducing test data volume using external/LBIST hybrid test patterns
D Das, NA Touba - … Test Conference 2000 (IEEE Cat. No …, 2000 - ieeexplore.ieee.org
A common approach for large industrial designs is to use logic built-in self-test (LBIST)
followed by test data from an external tester. Because the fault coverage with LBIST alone is …
followed by test data from an external tester. Because the fault coverage with LBIST alone is …
Bit-fixing in pseudorandom sequences for scan BIST
NA Touba, EJ McCluskey - IEEE Transactions on computer …, 2001 - ieeexplore.ieee.org
A low-overhead scheme for achieving complete (100%) fault coverage during built-in self
test of circuits with scan is presented. It does not require modifying the function logic and …
test of circuits with scan is presented. It does not require modifying the function logic and …
Total Synthesis of (-)-Colombiasin and (-)-Elisapterosin B
DC Harrowven, DD Pascoe, D Demurtas… - Synfacts, 2005 - thieme-connect.com
Significance: The target molecules were isolated from the gorgonian octocoral
Pseudopterogorgia elisabethae. Elisapterosin B is active against Plasmodium falciparum …
Pseudopterogorgia elisabethae. Elisapterosin B is active against Plasmodium falciparum …
Deeptpi: Test point insertion with deep reinforcement learning
Test point insertion (TPI) is a widely used technique for testability enhancement, especially
for logic built-in self-test (LBIST) due to its relatively low fault coverage. In this paper, we …
for logic built-in self-test (LBIST) due to its relatively low fault coverage. In this paper, we …
Special session: Survey of test point insertion for logic built-in self-test
This article surveys test point (TP) architectures and test point insertion (TPI) methods for
increasing pseudo-random and logic built-in self-test (LBIST) fault coverage. We present a …
increasing pseudo-random and logic built-in self-test (LBIST) fault coverage. We present a …