Formal modeling of network-on-chip using CFSM and its application in detecting deadlock
A formal modeling of a Network-on-Chip (NoC) using a communicating finite state machine
(CFSM) is presented in this article. We have automated the CFSM model generation for …
(CFSM) is presented in this article. We have automated the CFSM model generation for …
Accelerating NoC Verification Using a Complete Model and Active Window
This work presents formal modeling of Network-on-Chip (NoC) considering detailed
functional units of NoC. The intricate modeling of NoC router components like buffer, switch …
functional units of NoC. The intricate modeling of NoC router components like buffer, switch …
WickedXmas: Designing and verifying on-chip communication fabrics
In modern chip architectures, the increase in parallelization brings about highly complex on-
chip communication fabrics. We present WickedXmas, a tool that facilitates the design and …
chip communication fabrics. We present WickedXmas, a tool that facilitates the design and …
Compositional performance verification of NoC designs
DE Holcomb, A Gotmanov… - Tenth ACM/IEEE …, 2012 - ieeexplore.ieee.org
We present a compositional approach to formally verify quality-of-service (QoS) properties of
network-on-chip (NoC) designs. A major challenge to scalability is the need to verify latency …
network-on-chip (NoC) designs. A major challenge to scalability is the need to verify latency …
Automatic extraction of micro-architectural models of communication fabrics from register transfer level designs
SJC Joosten, J Schmaltz - 2015 Design, Automation & Test in …, 2015 - ieeexplore.ieee.org
Multi-core processors and Systems-on-Chips are composed of a large number of processing
and memory elements interconnected by complex communication fabrics. These fabrics are …
and memory elements interconnected by complex communication fabrics. These fabrics are …
A structured visual approach to GALS modeling and verification of communication circuits
F Burns, D Sokolov, A Yakovlev - IEEE Transactions on …, 2016 - ieeexplore.ieee.org
In this paper, a novel globally asynchronous locally synchronous (GALS) modeling and
verification tool is introduced for xMAS circuits. The tool provides a structured environment …
verification tool is introduced for xMAS circuits. The tool provides a structured environment …
Process algebra semantics & reachability analysis for micro-architectural models of communication fabrics
S Wouda, SJC Joosten… - 2015 ACM/IEEE …, 2015 - ieeexplore.ieee.org
We propose an algorithm for reachability analysis in micro-architectural models of
communication fabrics. The main idea of our solution is to group transfers in what we call …
communication fabrics. The main idea of our solution is to group transfers in what we call …
Formal modeling and verification of starvation freedom in nocs
Formal modeling plays a key role in verification of crucial properties of a complex system like
Network-on-Chip (NoC) before the actual hardware is manufactured. This work presents …
Network-on-Chip (NoC) before the actual hardware is manufactured. This work presents …
xMAS based accurate modeling and progress verification of NoCs
Abstract Network on Chip (NoC) plays a significant role in improving computation speed in
Tiled Chip Multiprocessor (TCMP) by acting as an efficient interconnection network between …
Tiled Chip Multiprocessor (TCMP) by acting as an efficient interconnection network between …
Formal verification and synthesis for quality-of-service in on-chip networks
DE Holcomb - 2013 - escholarship.org
Quality-of-service (QoS) in on-chip communication networks has a tremendous impact on
overall system performance in today's era of ever-increasing core counts. Yet, Networks-on …
overall system performance in today's era of ever-increasing core counts. Yet, Networks-on …