Investigation of multiple-valued logic technologies for beyond-binary era

ZT Sandhie, JA Patel, FU Ahmed… - ACM Computing Surveys …, 2021 - dl.acm.org
Computing technologies are currently based on the binary logic/number system, which is
dependent on the simple on and off switching mechanism of the prevailing transistors. With …

Comprehensive survey of ternary full adders: Statistics, corrections, and assessments

S Nemati, M Haghi Kashani… - IET Circuits, Devices & …, 2023 - Wiley Online Library
The history of ternary adders goes back to more than 6 decades ago. Since then, a multitude
of ternary full adders (TFAs) have been presented in the literature. This article conducts a …

A review on the design of ternary logic circuits

XY Wang, CT Dong, ZR Wu, ZQ Cheng - Chinese Physics B, 2021 - iopscience.iop.org
A multi-valued logic system is a promising alternative to traditional binary logic because it
can reduce the complexity, power consumption, and area of circuit implementation. This …

Implementation of digital competency-building strategy in management education

MA Quttainah, P Singh - Abhigyan, 2024 - journals.sagepub.com
This article uses a case study method to explore implementing an organisation's digital
competency-building strategy. The research examines the organisation's context, including …

Compact Model for a Negative Capacitance-Based Top-Gated Carbon-Nanotube Field-Effect Transistor

S Mairaj, A Singh - Journal of Electronic Materials, 2024 - Springer
This paper proposes a compact model for a top-gated negative capacitance-based carbon
nanotube field-effect transistor (NC-CNTFET). The proposed model relies on a metal …

Energy-efficient design and CNFET implementation of GDI-based ternary prefix adders

K Shanmugam, K Chandrasekaran… - Physica …, 2024 - iopscience.iop.org
Ternary adders have produced more benefits compared to binary adders ie, the ternary
adder occupies less amount of area as well as produces less interconnect complexity …

Comparative study of full adder circuit with 32nm MOSFET, DG-FinFET and CNTFET

SMI Huq, M Nafreen, T Rahman… - 2017 4th International …, 2017 - ieeexplore.ieee.org
In this paper, we study the performance of Full Adder circuit with three different FET devices,
MOSFET, Double-Gate (DG) FinFET and CNTFET, in 32nm technology. The full adder circuit …

PDP analysis of CNTFET full adders for single and multiple threshold voltages

M Elangovan, R Ranjith, S Devika - Advances in VLSI, Communication …, 2020 - Springer
Adder is a basic building block of the arithmetic logic unit (ALU). Designing of optimized
adder circuit inherently makes a pavement for obtaining optimized ALU design. The …

Design of quaternary inverter using 32nm SOI technology

D Sagar, SC Sannamani, KSV Patel… - … on Advances in …, 2023 - ieeexplore.ieee.org
In VLSI design due to continuous increase in chip density and decline in size of CMOS
technology node, number of interconnects become one of the major concern. To avoid …

Quaternary Digital Circuits Design Using Carbon Nano Tube Fets

TNJ Kolanti, PKS Vasundara - … International Conference on …, 2018 - ieeexplore.ieee.org
The quaternary Digital Circuits like MIN, MAX and literal circuits are presented in this paper.
The Carbon Nano Tube FET's (CNTFET) are used in MIN and MAX circuits that have been …