Operation apparatus and method for convolutional neural network

JIN Young-Jae, YS Moon, HS Kim - US Patent 11,449,745, 2022 - Google Patents
Disclosed herein is a convolutional neural network (CNN) operation apparatus, including at
least one channel hardware set suitable for performing a feature extraction layer operation …

A self-adaptive SEU mitigation system for FPGAs with an internal block RAM radiation particle sensor

R Glein, B Schmidt, F Rittner, J Teich… - 2014 IEEE 22nd …, 2014 - ieeexplore.ieee.org
In this paper, we propose a self-adaptive FPGA-based, partially reconfigurable system for
space missions in order to mitigate Single Event Upsets in the FPGA configuration and …

Scalable FPGA refurbishment using netlist-driven evolutionary algorithms

RA Ashraf, RF DeMara - IEEE Transactions on Computers, 2013 - ieeexplore.ieee.org
In this work, Field-Programmable Gate Array (FPGA) reconfigurability is exploited to realize
autonomous fault recovery in mission-critical applications at runtime. The proposed Netlist …

Designing and evaluating redundancy-based soft-error masking on a continuum of energy versus robustness

FS Alghareb, RA Ashraf… - IEEE Transactions on …, 2017 - ieeexplore.ieee.org
Near-threshold computing is an effective strategy to reduce the power dissipation of deeply-
scaled CMOS logic circuits. However, near-threshold strategies exacerbate the impact of …

Fault tolerant and energy efficient signal processing on FPGA using evolutionary techniques

D Jose, R Tamilselvan - … and Computational Models: Proceedings of ICC3 …, 2016 - Springer
In this paper, an energy efficient approach using field-programmable gate array (FPGA)
partial dynamic reconfiguration (PDR) is presented to realize autonomous fault recovery in …

Energy and delay tradeoffs of soft-error masking for 16-nm FinFET logic paths: Survey and impact of process variation in the near-threshold region

FS Alghareb, RA Ashraf, A Alzahrani… - IEEE Transactions on …, 2016 - ieeexplore.ieee.org
A near-threshold voltage (NTV) operation provides a recognized approach to low-power
circuit design due to its balancing of minor performance degradation relative to its significant …

Implementation of genetic algorithm framework for fault tolerant system on chip

D Jose, PN Kumar, JA Shirley… - International …, 2014 - search.proquest.com
In this article, a hardware/software platform using field programmable gate array (FPGA)
reconfigurability and genetic algorithm (GA) is presented, to realize autonomous fault …

Leveraging Signal Transfer Characteristics and Parasitics of Spintronic Circuits for Area and Energy-Optimized Hybrid Digital and Analog Arithmetic

A Tatulian - 2023 - stars.library.ucf.edu
Abstract While Internet of Things (IoT) sensors offer numerous benefits in diverse
applications, they are limited by stringent constraints in energy, processing area and …

Adaptive mitigation of radiation-induced errors and TDDB in reconfigurable logic fabrics

R Al-Haddad, RS Oreifej, R Zand… - 2015 IEEE 24th …, 2015 - ieeexplore.ieee.org
Self-reliance capabilities of mission-critical systems gain importance as technology scaling
and logic capacity of SRAM-based reconfigurable devices increase. The Sustainable …

Soft error effect tolerant temporal self-voting checkers: Energy vs. resilience tradeoffs

FS Alghareb, M Lin, RF DeMara - 2016 IEEE Computer Society …, 2016 - ieeexplore.ieee.org
Achieving high reliability against transient faults poses significant challenges due to the
trends of technology and voltage scaling. Thus, numerous soft error mitigation techniques …