(57) ABSTRACT A processor includes a plurality of processor tiles, each tile including a
processor core, and an interconnection network interconnects the processor cores and …

A multicore processor comprises a plurality of cache memories; a plurality of processor
cores, each associated with one of the cache memories; and a plurality of memory interfaces …

3,787,752 A 1/1974 Delay 4,859,911 A 8/1989 Kinnardet a1. 5,128,595 A 7/1992 Hara
5,661,645 A 8/1997 Hochstein 5,783,909 A 7/1998 Hochstein 6,016,038 A 1/2000 Mueller et …

An integrated circuit includes a plurality of processor core. Processing instructions in the
integrated circuit includes: managing a plurality of sets of processor cores, each set …

Pattern matching in a plurality of interconnected processing engines includes: accepting a
stream of input sequences over an interface and storing the input sequences; storing …

Aspects of the present disclosure relate to a method and system for hybrid and/or distributed
implementation of generation and/or execution of power profile management instructions …

Example implementations described herein are directed to a configurable building block,
such as a router, for implementation of a Network on Chip (NoC). The router is …

5.960, 461 A 9, 1999 Frank et al. comprising a computation unit and a memory. The
apparatus 6,332,178 B1 12/2001 Dean et al. further comprises an interconnection network …

The present invention relates to signal processing devices adapted for simultaneously
processing at least two threads in a multi-processing or multi-threading manner, to methods …

A plurality of processor tiles are provided, each processor tile including a processor core. An
interconnection network interconnects the processor cores and enables transfer of data …