Greengpu: A holistic approach to energy efficiency in gpu-cpu heterogeneous architectures

K Ma, X Li, W Chen, C Zhang… - 2012 41st international …, 2012 - ieeexplore.ieee.org
In recent years, GPU-CPU heterogeneous architectures have been increasingly adopted in
high performance computing, because of their capabilities of providing high computational …

A 4-GHz 300-mW 64-bit integer execution ALU with dual supply voltages in 90-nm CMOS

SK Mathew, MA Anders, B Bloechel… - IEEE Journal of Solid …, 2005 - ieeexplore.ieee.org
This paper describes a single-cycle 64-bit integer execution ALU fabricated in 90-nm dual-Vt
CMOS technology, operating at 4 GHz in the 64-bit mode with a 32-bit mode frequency of 7 …

Comparison of high-performance VLSI adders in the energy-delay space

VG Oklobdzija, BR Zeydel, HQ Dao… - … Transactions on Very …, 2005 - ieeexplore.ieee.org
In this paper, we motivate the concept of comparing very large scale integration adders
based on their energy-delay characteristics and present results of our estimation technique …

Silicon microdisk-based full adders for optical computing

Z Ying, Z Wang, Z Zhao, S Dhar, DZ Pan, R Soref… - Optics letters, 2018 - opg.optica.org
Due to the projected saturation of Moore's law, as well as the drastically increasing trend of
bandwidth with lower power consumption, silicon photonics has emerged as one of the most …

Electro-optic ripple-carry adder in integrated silicon photonics for optical computing

Z Ying, S Dhar, Z Zhao, C Feng, R Mital… - IEEE journal of …, 2018 - ieeexplore.ieee.org
Photonic integrated circuits with compact size and low power consumption have opened the
possibility of realization of ultrahigh-speed and energy-efficient optical computing in an …

Low vccmin fault-tolerant cache with highly predictable performance

J Abella, J Carretero, P Chaparro, X Vera… - Proceedings of the …, 2009 - dl.acm.org
Transistors per area unit double in every new technology node. However, the electric field
density and power demand grow if Vcc is not scaled. Therefore, Vcc must be scaled in pace …

Energy-efficient design methodologies: High-performance VLSI adders

BR Zeydel, D Baran… - IEEE Journal of solid-state …, 2010 - ieeexplore.ieee.org
Energy-efficient design requires exploration of available algorithms, recurrence structures,
energy and wire tradeoffs, circuit design techniques, circuit sizing and system constraints. In …

On modulo 2^ n+ 1 adder design

HT Vergos, G Dimitrakopoulos - IEEE transactions on …, 2010 - ieeexplore.ieee.org
Two architectures for modulo 2 n+ 1 adders are introduced in this paper. The first one is built
around a sparse carry computation unit that computes only some of the carries of the modulo …

Improving the speed of parallel decimal multiplication

G Jaberipur, A Kaivani - IEEE Transactions on Computers, 2009 - ieeexplore.ieee.org
Hardware support for decimal computer arithmetic is regaining popularity. One reason is the
recent growth of decimal computations in commercial, scientific, financial, and Internet …

[图书][B] Introduction to VLSI systems: a logic, circuit, and system perspective

MB Lin - 2011 - taylorfrancis.com
With the advance of semiconductors and ubiquitous computing, the use of system-on-a-chip
(SoC) has become an essential technique to reduce product cost. With this progress and …