In this work, a sense amplifier based flip flop (SAFF) is presented appropriate for high speed,
high data activity and low power operations. The delay and power of the proposed flip flop …

This paper investigates the metastability of true single-phase clock (TSPC) D flip flops
(DFFs) and its impact on the resolution of Vernier time-to-digital converters (TDCs). The …

This paper provide a comparative study of design techniques for bootstrapping in the
sample-and-hold of energy-efficient successive approximation register analog-to-digital …

This paper provides a comparative study of bootstrapping techniques in energy-efficient
successive approximation register analog-to-digital converters (SAR ADCs). The need for …

A Sense Amplifier based flip-flop (SAFF) capable of operating unfailingly at wide voltage
and temperature ranges is proposed in this work. The proposed flip-flop (FF) has a single …

This paper provides an in-depth treatment of voltage-to-time converters (VTCs) for time-
based signal processing with a nonlinearity emphasis. The need for VTCs in deployment of …

This paper investigates the metastability of true-singlephase-clock (TSPC) D flipflops (DFFs).
The cause of the metastability of the DFFs, both positive edge-triggered (PET) and negative …

In this paper, a sense-amplifier-based flip-flop (SAFF) suitable for low-power high-speed
operation is proposed. With the employment of a new sense-amplifier stage as well as a …

This paper proposes an all-digital bi-directional gated ring oscillator (BDGRO) time
integrator for mixed-mode signal processing. The proposed time integrator features full …

Advancement in technology towards mobile computing and communication demands longer
battery life, which mandates the low power design methodologies. In this paper, we have …