Memory bus encoding for low power: a tutorial

WC Cheng, M Pedram - Proceedings of the IEEE 2001. 2nd …, 2001 - ieeexplore.ieee.org
This paper contains a tutorial on bus-encoding techniques that target low power dissipation.
Three general classes of codes, ie, algebraic, permutation-based, and probability-based …

A survey of encoding techniques for reducing data-movement energy

S Mittal, S Nag - Journal of Systems Architecture, 2019 - Elsevier
In modern processors, data-movement consumes two orders of magnitude higher energy
than a floating-point operation and hence, data-movement is becoming the primary …

[图书][B] On-chip communication architectures: system on chip interconnect

S Pasricha, N Dutt - 2010 - books.google.com
Over the past decade, system-on-chip (SoC) designs have evolved to address the ever
increasing complexity of applications, fueled by the era of digital convergence …

System-level power-aware design techniques in real-time systems

OS Unsal, I Koren - Proceedings of the IEEE, 2003 - ieeexplore.ieee.org
Power and energy consumption has recently become an important issue and consequently,
power-aware techniques are being devised at all levels of system design; from the circuit …

Data encoding techniques for reducing energy consumption in network-on-chip

N Jafarzadeh, M Palesi… - … Transactions on Very …, 2013 - ieeexplore.ieee.org
As technology shrinks, the power dissipated by the links of a network-on-chip (NoC) starts to
compete with the power dissipated by the other elements of the communication subsystem …

Irredundant address bus encoding for low power

Y Aghaghiri, F Fallah, M Pedram - … on Low power electronics and design, 2001 - dl.acm.org
This paper proposes efficient encoding techniques for decreasing power dissipation on
global buses. The best target for these techniques is a wide and highly capacitive memory …

Low-power bus encoding with crosstalk delay elimination

CG Lyuh, T Kim - IEE proceedings-computers and digital techniques, 2006 - IET
In deep-submicron technology, minimising the propagation delay and power consumption
on buses is the most important design objective in system-on-chip design. In particular, the …

A sensitivity-based design space exploration methodology for embedded systems

W Fornaciari, D Sciuto, C Silvano… - Design Automation for …, 2002 - Springer
In this paper, we propose a system-level design methodology for the efficient exploration of
the architectural parameters of the memory sub-systems, from the energy-delay joint …

Efficient RC low-power bus encoding methods for crosstalk reduction

CP Fan, CH Fang - Integration, 2011 - Elsevier
In on-chip buses, the RC crosstalk effect leads to serious problems, such as wire
propagation delay and dynamic power dissipation. This paper presents two efficient bus …

Power-optimal encoding for DRAM address bus

WC Cheng, M Pedram - … of the 2000 international symposium on Low …, 2000 - dl.acm.org
This paper presents Pyramid code, an optimal code for transmitting sequential addresses
over a DRAM bus. Constructed by finding an Eulerian cycle on a complete graph, this code …