A distributed instruction queue (DIQ) in a superscalar microprocessor supports multi-
instruction issue, decoupled data flow scheduling, out-of-order execution, register renaming …

A register is a high Speed temporary memory device used to receive, hold, and transfer data
(usually a computer word) to be operated upon by a processing unit. Registers provide …

4,992,933 2/1991 Cocke et a1_ ______ u 395/375 addressable sizes as sources and
destinations of operands for 5,197,132 3/1993 Steely, Jr. et a1... 3951375 the instruction. A …

Zafman 57 ABSTRACT A method and apparatus for executing floating point and packed
data instructions using a Single physical register file that is aliased. According to one aspect …

(57) ABSTRACT A facility is provided for managing register maps for map based indirect
register file access within a processor. The management facility includes a register mapping …

Bracewell & Patterson LLP (57) ABSTRACT A method and a System in a data processing
System for managing registers in a register array wherein the data processing System has …

57 ABSTRACT A high-performance, SuperScalar-based computer System with out-of-order
instruction execution for enhanced resource utilization and performance throughput. The …

4,752,873 6/1988 Shonai et al.. 4,829,425 5/1989 Bain, Jr. et al.. trolling the flow of
instructions through the pipelines Such that an instruction is not delayed due to a data …

In a microprocessor, an apparatus is included for coordinat ing the use of physical registers
in the microprocessor. Upon receiving an instruction, the coordination apparatus extracts …

A superscalar superpipelined microprocessor having a write buffer located between the core
and cache is disclosed. The write buffer is controlled to store the results of write operations …