H Dwyer III, HR McLellan - US Patent 5,996,068, 1999 - Google Patents
A register is a high Speed temporary memory device used to receive, hold, and transfer data (usually a computer word) to be operated upon by a processing unit. Registers provide …
M Bluhm - US Patent 5,630,149, 1997 - Google Patents
4,992,933 2/1991 Cocke et a1_ ______ u 395/375 addressable sizes as sources and destinations of operands for 5,197,132 3/1993 Steely, Jr. et a1... 3951375 the instruction. A …
D Lin, RR Vakkalagadda, AF Glew… - US Patent …, 1998 - Google Patents
Zafman 57 ABSTRACT A method and apparatus for executing floating point and packed data instructions using a Single physical register file that is aliased. According to one aspect …
PG Capek, JH Derby, RK Montoye - US Patent 7,631,167, 2009 - Google Patents
(57) ABSTRACT A facility is provided for managing register maps for map based indirect register file access within a processor. The management facility includes a register mapping …
CM Chuang, HQ Le - US Patent 6,356,918, 2002 - Google Patents
Bracewell & Patterson LLP (57) ABSTRACT A method and a System in a data processing System for managing registers in a register array wherein the data processing System has …
DJ Lentz, Y Miyayama, S Garg, Y Hagiwara… - US Patent …, 1999 - Google Patents
57 ABSTRACT A high-performance, SuperScalar-based computer System with out-of-order instruction execution for enhanced resource utilization and performance throughput. The …
MW Hervin, SC McMahan, M Bluhm… - US Patent …, 2000 - Google Patents
4,752,873 6/1988 Shonai et al.. 4,829,425 5/1989 Bain, Jr. et al.. trolling the flow of instructions through the pipelines Such that an instruction is not delayed due to a data …
MC Shebanow, GW Shen, R Swami… - US Patent …, 1997 - Google Patents
In a microprocessor, an apparatus is included for coordinat ing the use of physical registers in the microprocessor. Upon receiving an instruction, the coordination apparatus extracts …
MA Quattromani, RA Garibay Jr, N Patwa… - US Patent …, 1995 - Google Patents
A superscalar superpipelined microprocessor having a write buffer located between the core and cache is disclosed. The write buffer is controlled to store the results of write operations …