A 7nm CMOS technology platform for mobile and high performance compute application

S Narasimha, B Jagannathan, A Ogino… - 2017 IEEE …, 2017 - ieeexplore.ieee.org
We present a fully integrated 7nm CMOS platform featuring a 3 rd generation finFET
architecture, SAQP for fin formation, and SADP for BEOL metallization. This technology …
被引用次数：66 相关文章 所有 3 个版本

Highly manufacturable 7nm FinFET technology featuring EUV lithography for low power and high performance applications

D Ha, C Yang, J Lee, S Lee, SH Lee… - 2017 Symposium on …, 2017 - ieeexplore.ieee.org
7nm CMOS FinFET technology featuring EUV lithography, 4 th gen. dual Fin and 2 nd gen.
multi-eWF gate stack is presented, providing 20% faster speed or consuming 35% less total …
被引用次数：80 相关文章

A 7nm FinFET SRAM using EUV lithography with dual write-driver-assist circuitry for low-voltage applications

T Song, J Jung, W Rim, H Kim, Y Kim… - … Solid-State Circuits …, 2018 - ieeexplore.ieee.org
SRAM plays an integral role in the power, performance, and area of a mobile system-on-a-
chip. To achieve low power and high density, extreme ultraviolet (EUV) technology is …
被引用次数：72 相关文章 所有 2 个版本

High performance 14nm SOI FinFET CMOS technology with 0.0174µm2 embedded DRAM and 15 levels of Cu metallization

CH Lin, B Greene, S Narasimha, J Cai… - 2014 IEEE …, 2014 - ieeexplore.ieee.org
We present a fully integrated 14nm CMOS technology featuring finFET architecture on an
SOI substrate for a diverse set of SoC applications including HP server microprocessors and …
被引用次数：183 相关文章 所有 4 个版本

5nm CMOS Production Technology Platform featuring full-fledged EUV, and High Mobility Channel FinFETs with densest 0.021µm2 SRAM cells for Mobile SoC and …

G Yeap, SS Lin, YM Chen, HL Shang… - 2019 IEEE …, 2019 - ieeexplore.ieee.org
A leading edge 5nm CMOS platform technology has been defined and optimized for mobile
and HPC applications. This industry-leading 5nm technology features, for the first time, full …
被引用次数：194 相关文章 所有 2 个版本

True 7nm Platform Technology featuring Smallest FinFET and Smallest SRAM cell by EUV, Special Constructs and 3rd Generation Single Diffusion Break

WC Jeong, S Maeda, HJ Lee, KW Lee… - … IEEE Symposium on …, 2018 - ieeexplore.ieee.org
7nm platform technology that takes full advantage of EUV lithography was developed, where
EUV was straightforwardly used for single patterning of MOL and BEOL, not just as a means …
被引用次数：50 相关文章 所有 2 个版本

Intel 4 CMOS technology featuring advanced FinFET transistors optimized for high density and high-performance computing

B Sell, S An, J Armstrong, D Bahr… - … IEEE Symposium on …, 2022 - ieeexplore.ieee.org
A new advanced CMOS FinFET technology, Intel 4, is introduced that extends Moore's law
by offering 2X area scaling of the high performance logic library and greater than 20 …
被引用次数：22 相关文章

A 4.6GHz 162Mb SRAM design in 22nm tri-gate CMOS technology with integrated active VMIN-enhancing assist circuitry

E Karl, Y Wang, YG Ng, Z Guo… - … Solid-State Circuits …, 2012 - ieeexplore.ieee.org
Future product applications demand increasing performance with reduced power
consumption, which motivates the pursuit of high-performance at reduced operating …
被引用次数：231 相关文章 所有 3 个版本
[PDF] researchgate.net

Demonstration of scaled 0.099µm2 FinFET 6T-SRAM cell using full-field EUV lithography for (Sub-)22nm node single-patterning technology

A Veloso, S Demuynck, M Ercken… - 2009 IEEE …, 2009 - ieeexplore.ieee.org
We demonstrate electrically functional 0.099 μm 2 6T-SRAM cells using full-field EUV
lithography for contact and M1 levels. This enables formation of dense arrays without …
被引用次数：35 相关文章 所有 6 个版本

Si FinFET based 10nm technology with multi Vt gate stack for low power and high performance applications

HJ Cho, HS Oh, KJ Nam, YH Kim… - … IEEE Symposium on …, 2016 - ieeexplore.ieee.org
10nm logic technology using Si FinFET is developed for low power and high performance
applications. Power-speed gain of 27% compared to 14nm technology node was obtained …
被引用次数：84 相关文章