Power consumption of a circuit is more in test mode than normal mode. The increased heat
due to excess power dissipation can open up reliability issue due to electro-migration. In …

In this paper, a new scan flip-flop is proposed for low power testing. Different flip-flops
(Master-slave, hybrid, pulse triggered) are reviewed and evaluated their performance using …

We present a technique to reduce the power of combinational circuits during testing. Power
dissipation of IC during test mode is greater than the IC's normal mode of functioning. During …

Power consumption of very large scale integrated (VLSI) systems is much higher during
testing as a result of increased circuit activity. This paper presents a novel low-power D flip …

Power consumption of any circuit is high during test mode than its normal mode of
functioning. Different techniques are proposed to reduce the test power. This paper presents …

Over the years, The semiconductor industry has made tremendously impressive
improvement in terms of density of very large-scale integrated (VLSI) circuits. Increasing …

Low-power devices are indispensable for modern electronic applications, and numerous
hardware/software techniques have been developed for drastically reducing functional …

The System-On-Chip (SoC) revolution challenges both design and test engineers,
especially in the area of power dissipation. Generally, a circuit or system consumes more …

The power consumption of modern highly complex chips during scan test is significantly
higher than the power consumed during functional mode. This leads to substantial heat …

This paper proposes a low power scan test scheme and formulates a problem based on this
scheme. In this scheme the flip-flops are grouped into N scan chains. At any time, only one …