Most work to date on power reduction has focused at the component level, not at the system
level. In this paper, we propose a framework for describing the power behavior of system …

Most work to date on power reduction has focused at the component level, not at the system
level. In this paper, we propose a framework for describing the power behavior of system …

Most work to date on power reduction has focused at the component level, not at the system
level. In this paper, we propose a framework for describing the power behavior of system …

We introduce the design methodology known as dynamic power management (DPM),
targeting the maximization of power efficiency under performance constraints for electronic …

Dynamic power management schemes (also called policies) can be used to control the
power consumption levels of electronic systems, by setting their components in different …

One of the most important considerations for the current VLSI/SOC design is power, which
can be classified into power analysis and optimization. In this survey, the main concepts of …

Reducing power consumption is a challenge to system designers. Portable systems, such as
laptop computers and personal digital assistants (PDAs), draw power from batteries, so …

We propose a new DVFS algorithm for enterprise systems that elevates performance as a
first order control parameter and manages frequency and voltage as a function of …

This paper discusses several of the SOC design issues pertaining to dynamic voltage and
frequency scalable systems, and how these issues were resolved in the IBM PowerPC …

System-level power management has been studied extensively. For further energy
reduction, the collaboration from user applications becomes critical. This paper presents a …