Full bottom dielectric isolation to enable stacked nanosheet transistor for low power and high performance applications
In this paper, full bottom dielectric isolation (BDI) is first demonstrated on horizontally
stacked Nanosheet device structures with Lmetal 12 nm. The comparison of full BDI scheme …
stacked Nanosheet device structures with Lmetal 12 nm. The comparison of full BDI scheme …
Vertical-transport nanosheet technology for CMOS scaling beyond lateral-transport devices
H Jagannathan, B Anderson, CW Sohn… - 2021 IEEE …, 2021 - ieeexplore.ieee.org
We demonstrate, for the first time, Vertical-Transport Nanosheet (VTFET) CMOS logic
transistors at sub-45nm gate pitch on bulk silicon wafers. We show that VTFETs present an …
transistors at sub-45nm gate pitch on bulk silicon wafers. We show that VTFETs present an …
Punch-through-stopper free nanosheet FETs with crescent inner-spacer and isolated source/drain
Structural modifications of 5-nm node nanosheet FETs (NSFETs) were quantitatively
analyzed using fully calibrated TCAD. The NSFETs with crescent inner spacer improve the …
analyzed using fully calibrated TCAD. The NSFETs with crescent inner spacer improve the …
Design and optimization of triple-k spacer structure in two-stack nanosheet FET from OFF-state leakage perspective
In this article, a 5-nm node two-stack nanosheet FET with a triple-k spacer structure
representing three spacer regions consisting of two inner spacers (inner spacer 1 and inner …
representing three spacer regions consisting of two inner spacers (inner spacer 1 and inner …
Leakage optimization of the buried oxide substrate of nanosheet field-effect transistors
S Yoo, S Kim - IEEE Transactions on Electron Devices, 2022 - ieeexplore.ieee.org
In this work, a new buried oxide nanosheet field-effect transistor (BO-NSFET) structure is
proposed for the first time as a strategy for improving the leakage of 3-nm stacked nanosheet …
proposed for the first time as a strategy for improving the leakage of 3-nm stacked nanosheet …
A novel dry selective etch of SiGe for the enablement of high performance logic stacked gate-all-around nanosheet devices
In this paper, we demonstrate a first of a kind SiGe dry etch technique for the formation of
inner spacers and for channel release, enabling stacked NanoSheet (NS) gate-all-around …
inner spacers and for channel release, enabling stacked NanoSheet (NS) gate-all-around …
Optimization of design space for vertically stacked junctionless nanosheet FET for analog/RF applications
This paper investigates the various device dimensions such as gate length (Lg), nanosheet
thickness (TNS), and nanosheet width to optimize the design space for vertically stacked …
thickness (TNS), and nanosheet width to optimize the design space for vertically stacked …
Novel trench inner-spacer scheme to eliminate parasitic bottom transistors in silicon nanosheet FETs
A novel and feasible trench inner-spacer (TIS) scheme to eliminate undesired parasitic
bottom transistors (trpbt) in gate-all-around (GAA) nanosheet (NS) field-effect transistors …
bottom transistors (trpbt) in gate-all-around (GAA) nanosheet (NS) field-effect transistors …
A review of the gate-all-around nanosheet FET process opportunities
S Mukesh, J Zhang - Electronics, 2022 - mdpi.com
In this paper, the innovations in device design of the gate-all-around (GAA) nanosheet FET
are reviewed. These innovations span enablement of multiple threshold voltages and …
are reviewed. These innovations span enablement of multiple threshold voltages and …
Multiple-Vt solutions in nanosheet technology for high performance and low power applications
In Nanosheet (NS) device architecture, it is much more challenging than FinFET to develop
a suitable multiple threshold voltage (multi-Vt) integration with more restrictive requirement …
a suitable multiple threshold voltage (multi-Vt) integration with more restrictive requirement …