Compiler-assisted preferred caching for embedded systems with STT-RAM based hybrid cache
As technology scales down, energy consumption is becoming a big problem for traditional
SRAM-based cache hierarchies. The emerging Spin-Torque Transfer RAM (STT-RAM) is a …
SRAM-based cache hierarchies. The emerging Spin-Torque Transfer RAM (STT-RAM) is a …
Compiler-assisted STT-RAM-based hybrid cache for energy efficient embedded systems
Hybrid caches consisting of static RAM (SRAM) and spin-torque transfer (STT)-RAM have
been proposed recently for energy efficiency. To explore the advantages of hybrid cache …
been proposed recently for energy efficiency. To explore the advantages of hybrid cache …
Migration-aware loop retiming for STT-RAM-based hybrid cache in embedded systems
Recently hybrid cache architecture consisting of both spin-transfer torque RAM (STT-RAM)
and SRAM has been proposed for energy efficiency. In hybrid caches, migration-based …
and SRAM has been proposed for energy efficiency. In hybrid caches, migration-based …
Compiler-assisted refresh minimization for volatile STT-RAM cache
Spin-transfer torque RAM (STT-RAM) has been proposed to build on-chip caches because
of its attractive features such as high storage density and ultra low leakage power. However …
of its attractive features such as high storage density and ultra low leakage power. However …
Prediction hybrid cache: An energy-efficient STT-RAM cache architecture
Spin-transfer torque RAM (STT-RAM) has emerged as an energy-efficient and high-density
alternative to SRAM for large on-chip caches. However, its high write energy has been …
alternative to SRAM for large on-chip caches. However, its high write energy has been …
HALLS: An energy-efficient highly adaptable last level STT-RAM cache for multicore systems
K Kuan, T Adegbija - IEEE Transactions on Computers, 2019 - ieeexplore.ieee.org
Spin-Transfer Torque RAM (STT-RAM) is widely considered a promising alternative to
SRAM in the memory hierarchy due to STT-RAM's non-volatility, low leakage power, high …
SRAM in the memory hierarchy due to STT-RAM's non-volatility, low leakage power, high …
Architecture and data migration methodology for L1 cache design with hybrid SRAM and volatile STT-RAM configuration
WK Cheng, YH Ciou, PY Shen - Microprocessors and Microsystems, 2016 - Elsevier
Abstract Spin-Transfer Torque RAM (STT-RAM) has the advantages of circuit density and
ignorable leakage power. However, it suffers from the bad write latency and poor write …
ignorable leakage power. However, it suffers from the bad write latency and poor write …
Mirrorcache: An energy-efficient relaxed retention l1 sttram cache
K Kuan, T Adegbija - Proceedings of the 2019 on Great Lakes …, 2019 - dl.acm.org
Spin-Transfer Torque RAM (STTRAM) is a promising alternative to SRAMs in on-chip
caches, due to several advantages, including non-volatility, low leakage, high integration …
caches, due to several advantages, including non-volatility, low leakage, high integration …
Low-energy volatile STT-RAM cache design using cache-coherence-enabled adaptive refresh
Spin-Torque Transfer RAM (STT-RAM) is a promising candidate for SRAM replacement
because of its excellent features, such as fast read access, high density, low leakage power …
because of its excellent features, such as fast read access, high density, low leakage power …
Energy-efficient runtime adaptable L1 STT-RAM cache design
K Kuan, T Adegbija - … on Computer-Aided Design of Integrated …, 2019 - ieeexplore.ieee.org
Much research has shown that applications have variable runtime cache requirements. In
the context of the increasingly popular spin-transfer torque RAM (STT-RAM) cache, the …
the context of the increasingly popular spin-transfer torque RAM (STT-RAM) cache, the …