Aggressive use of deep sleep mode in low power embedded systems
J Segawa, Y Shirota, K Fujisaki… - 2014 IEEE COOL …, 2014 - ieeexplore.ieee.org
Since idle-state is the dominant state for embedded systems, disabling unused devices in
idle-states can lead to significant power reduction. Among the various sleep modes provided …
idle-states can lead to significant power reduction. Among the various sleep modes provided …
Hypnos: An ultra-low power sleep mode with SRAM data retention for embedded microcontrollers
In heavily duty-cycled embedded systems, the energy consumed by the microcontroller in
idle mode is often the bottleneck for battery lifetime. Existing solutions address this problem …
idle mode is often the bottleneck for battery lifetime. Existing solutions address this problem …
Challenges in sleep transistor design and implementation in low-power designs
K Shi, D Howard - Proceedings of the 43rd annual Design Automation …, 2006 - dl.acm.org
Optimum power gating sleep transistor design and implementation are critical to a
successful low-power design. This paper describes important considerations for the sleep …
successful low-power design. This paper describes important considerations for the sleep …
A smart iot system for continuous sleep state monitoring
VL Ramnath, S Katkoori - 2020 IEEE 63rd International Midwest …, 2020 - ieeexplore.ieee.org
Sleep is a vital process in the maintenance of health and well-being. The effects of poor or
deprived sleep can have a major impact on the daily, healthy functioning of the human body …
deprived sleep can have a major impact on the daily, healthy functioning of the human body …
Design of general purpose microprocessor with an improved performance self-sleep circuit
ER Thuraka, R Katreepalli… - … Conference on Smart …, 2018 - ieeexplore.ieee.org
As the technology advances leakage power is a major concern to be addressed. MTCMOS
technique has been the finest technique to decrease significant power in standby mode …
technique has been the finest technique to decrease significant power in standby mode …
Optimized sleep mode operation
A Toskala, M Aksentijevic, OA Lehtinen - 2001 - Google Patents
First worldwide family litigation filed litigation Critical https://patents. darts-ip. com/? family=
8557057&utm_source= google_patent&utm_medium= platform_link&utm_campaign …
8557057&utm_source= google_patent&utm_medium= platform_link&utm_campaign …
Stepwise sleep depth control for run-time leakage power saving
S Takeda, S Miwa, K Usami, H Nakamura - Proceedings of the great …, 2012 - dl.acm.org
Recently, run-time sleep control scheme using multiple sleep modes have been studied. In
those studies, each sleep mode has its own sleep depth. Deeper sleep mode provides …
those studies, each sleep mode has its own sleep depth. Deeper sleep mode provides …
Dynamic sleep for multicore computing devices
TA Ulmer, AJ Frantz, NS Gargash, M Abel - 2021 - Google Patents
Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL
TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL …
TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL …
Sleep Convention Logic using partially slept function blocks
P Palangpour, SC Smith - 2013 IEEE 56th International …, 2013 - ieeexplore.ieee.org
Sleep Convention Logic (SCL) is a self-timed pipeline style that offers inherent power-
gating, resulting in ultra-low static power consumption. After each pipeline stage has …
gating, resulting in ultra-low static power consumption. After each pipeline stage has …