Dynamic power consumption is a critical concern in the design of both high performance
and low-power circuits. Clock-gating is one of the most efficient and prominent approaches …

Dynamic power saving is gaining its dominance in modern low power designs, while clock
gating, which blocks unnecessary clock switching activities, is one of the most efficient …

The Better-Than-Worst-Case (BTW) design methodology is well-known for its potential to
improve circuit energy efficiency, performance, and reliability. However, most existing …

Traditionally, clock gating for power saving is mainly done at Register Transistor Level
(RTL), while in a lower logical level some synthesis techniques, eg Observability Don't Care …

Clock gating is a power reduction technique for digital circuits that works by eliminating
unnecessary switching of parts of the clock network, a power-hungry component in …

A possible solution to handle the rising complexity of modern Systems-on-Chip (SoCs) is to
raise the level of abstraction for the design and optimization. A better optimization of …

The better-than-worst-case (BTW) design methodology can achieve higher circuit energy
efficiency, performance, or reliability by allowing timing errors for rare cases and rectifying …

The power gating technique is useful in reducing standby leakage current, but it increases
the gate delay. For a functional unit, its maximum allowable delay (for a target clock period) …

Comparing CMOS logic with pass-transistor logic, a question was raised in the minds of the
authors:" does any rule exist that contains all good?" This paper reveals novel logic …

Clock-gating and power-gating have proven to be very effective solutions for reducing
dynamic and static power, respectively. The two techniques may be coupled in such a way …