The capacity and cost-per-bit of DRAM have historically scaled to satisfy the needs of
increasingly large and complex computer systems. However, DRAM latency has remained …

In current systems, memory accesses to a DRAM chip must obey a set of minimum latency
restrictions specified in the DRAM standard. Such timing parameters exist to guarantee …

DRAM is the primary technology used for main memory in modern systems. Unfortunately,
as DRAM scales down to smaller technology nodes, it faces key challenges in both data …

DRAM is the prevalent main memory technology, but its long access latency can limit the
performance of many workloads. Although prior works provide DRAM designs that reduce …

The widespread use of multicore processors has dramatically increased the demand on
high memory bandwidth and large memory capacity. As DRAM subsystem designs stretch to …

This paper introduces a new DRAM design that enables fast and energy-efficient bulk data
movement across subarrays in a DRAM chip. While bulk data movement is a key operation …

DRAM latency is a major bottleneck for many applications in modern computing systems. In
this work, we rigorously characterize the effects of reducing DRAM access latency on 282 …

Modern DRAM cells are periodically refreshed to prevent data loss due to leakage.
Commodity DDR (double data rate) DRAM refreshes cells at the rank level. This degrades …

Over the past two decades, the storage capacity and access bandwidth of main memory
have improved tremendously, by 128x and 20x, respectively. These improvements are …

Technology scaling has continuously improved the density, performance, energy efficiency,
and cost of DRAM-based main memory systems. Starting from sub-20nm processes …