A physics-based model for LER-induced threshold voltage variations in double-gate MOSFET
The line-edge roughness (LER) has become one of the dominant sources of process
variations in multi-gate transistors. The estimation of threshold voltage distribution due to …
variations in multi-gate transistors. The estimation of threshold voltage distribution due to …
Study of Line Edge Roughness Induced Threshold Voltage Fluctuations in Double-Gate MOSFET
The statistical variability in nano-scaled devices due to line-edge roughness (LER) is a
major challenge for further scaling of device dimensions in multi-gate FETs. The LER in …
major challenge for further scaling of device dimensions in multi-gate FETs. The LER in …
Understanding LER-Induced MOSFET Variability—Part I: Three-Dimensional Simulation of Large Statistical Samples
In this paper, using computationally intensive 3-D simulations in a grid computing
environment, we perform a detailed study of line-edge-roughness (LER)-induced threshold …
environment, we perform a detailed study of line-edge-roughness (LER)-induced threshold …
TCAD-based statistical analysis and modeling of gate line-edge roughness effect on nanoscale MOS transistor performance and scaling
SD Kim, H Wada, JCS Woo - IEEE transactions on …, 2004 - ieeexplore.ieee.org
The effects of line edge roughness (LER) of nanometer scale gate pattern on the MOS
transistor parameter fluctuations and their technology scaling are investigated using the …
transistor parameter fluctuations and their technology scaling are investigated using the …
Understanding LER-Induced MOSFET Variability—Part II: Reconstructing the Distribution
In this paper, we examine, in more detail, the strong correlation between the distribution of
threshold voltage (VT) and the average channel length (L̅ C ̅) discovered in Part I of this …
threshold voltage (VT) and the average channel length (L̅ C ̅) discovered in Part I of this …
An experimentally validated analytical model for gate line-edge roughness (LER) effects on technology scaling
CH Diaz, HJ Tao, YC Ku, A Yen… - IEEE Electron device …, 2001 - ieeexplore.ieee.org
This letter introduces an analytical model to represent line-edge roughness (LER) effects on
both off-state leakage and drive current for sub-100-nm devices. The model partitions a …
both off-state leakage and drive current for sub-100-nm devices. The model partitions a …
Transistor width dependence of LER degradation to CMOS device characteristics
J Wu, J Chen, K Liu - International Conference on Simulation of …, 2002 - ieeexplore.ieee.org
When transistor gate length is scaled down, the impact of transistor poly gate line edge
roughness (LER) on device characteristics becomes significant. In this work, we study the …
roughness (LER) on device characteristics becomes significant. In this work, we study the …
3-D quasi-atomistic model for line edge roughness in nonplanar MOSFETs
As the physical sizes of devices have been scaled down, the negative impact of process-
induced random variation on device performance has increased; therefore, there is an …
induced random variation on device performance has increased; therefore, there is an …
Understanding LER-induced statistical variability: A 35,000 sample 3D simulation study
We study, in detail, statistical threshold voltage variability in a state of the art n-channel
MOSFET introduced by line edge roughness. A large sample of 35,000 transistors with …
MOSFET introduced by line edge roughness. A large sample of 35,000 transistors with …
Line edge roughness induced threshold voltage variability in nano-scale FinFETs
In aggressively scaled devices, the FinFET technology has become more prone to line edge
roughness (LER) induced threshold voltage variability. As a result, nano scale FinFET …
roughness (LER) induced threshold voltage variability. As a result, nano scale FinFET …