This paper describes the integration of a silicon carbon nitride (SiCN) copper passivation
and etch stop layer into a Cu low k dielectric interconnect technology. The incorporation of …

Conventional Cu-ULK integration schemes lead to a drastic increase of the dielectric
constant due to porous material degradation during process steps. In this paper, a post …

The integration challenges of a low-k dielectric (k< 3) to form multi-level Cu interconnects for
the next generation 0.1/spl mu/m CMOS technology are presented. Process improvements …

Copper interconnects have gained wide acceptance in the microelectronics industry due to
improved resistivity and reliability compared to Al interconnects. Initially SiO2 was used as …

A new model to predict percentage of performance improvement using copper and/or
low/spl kappa/is rigorously derived. Based on the new model, it is shown that for a typical …

This paper discusses the development of 300 mm CVD low-k dielectric for the 0.13/spl mu/m
technology Cu/low-k integration. A carbon doped oxide SiOC low-k dielectric was deposited …

Copper/low-k dielectric materials have been rapidly replacing conventional aluminum-
alloy/SiO 2-based interconnects in today's semiconductor devices. This paper reviews the …

This paper describes a comprehensive characterization of a 65 nm, 300 mm wafer size
interconnect technology with SiCOH material (k= 2.8). Excellent film properties of the SiCOH …

A novel CoWP cap integration technology for lower leakage current and improved dielectric
reliability is proposed for porous low-k/Cu interconnects, NH 3 plasma treatment before …

A highly reliable interface using a self-aligned CuSiN process with low-k SiC barrier
dielectric (k= 3.5) has been developed for 65nm node and beyond. Using this process as the …