DRAM latency continues to be a critical bottleneck for system performance. In this work, we
develop a low-cost mechanism, called Charge Cache, that enables faster access to recently …

DRAM has been the dominant technology for architecting main memory for decades. Recent
trends in multi-core system design and large-dataset applications have amplified the role of …

This paper describes a comprehensive approach for using the memory controller to improve
DRAM energy efficiency and manage DRAM power. We make three contributions:(1) we …

Power consumption and DRAM latencies are serious concerns in modern chip-
multiprocessor (CMP or multi-core) based compute systems. The management of the DRAM …

We re-think DRAM power modes by modeling and characterizing inter-arrival times for
memory requests to determine the properties an ideal power mode should have. This …

The DRAM main memory system in modern servers is largely homogeneous. In recent
years, DRAM manufacturers have produced chips with vastly differing latency and energy …

This paper analyzes the design trade-offs in architecting large-scale DRAM caches. Prior
research, including the recent work from Loh and Hill, have organized DRAM caches similar …

Efficient cache tag management is a primary design objective for large, in-package DRAM
caches. Recently, Tagless DRAM Caches (TDCs) have been proposed to completely …

Recent research advocates large die-stacked DRAM caches in many core servers to break
the memory latency and bandwidth wall. To realize their full potential, die-stacked DRAM …

Long DRAM access latency is a major bottleneck for system performance. In order to access
data in DRAM, a memory controller (1) activates (ie, opens) a row of DRAM cells in a cell …